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Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency

DC
  • US 5,091,846 A
  • Filed: 10/30/1989
  • Issued: 02/25/1992
  • Est. Priority Date: 10/03/1986
  • Status: Expired due to Term
First Claim
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1. A computer system comprising:

  • a primary memory for storing pages of data;

    a system bus coupled to the primary memory;

    a first data processing element coupled to the system bus for processing data from the primary memory;

    a second data processing element for processing data from the primary memory;

    cache memory management means, coupled to said second data processing element and to said system bus, including;

    a cache memory for storing data from said primary memory wherein data from the primary memory stored in the cache memory is accessed by the first and second data processing elements;

    a cache controller for providing real address translation for virtual addresses received from the second data processing element, for selectively storing and retrieving data to and from said cache memory, and for communicating data between the cache memory and the second data processing element; and

    system tag means for storing a system tag which indicates one of a plurality of cache data storage modes;

    wherein said cache controller includes;

    cache mode effecting means for effecting the cache data storage mode indicated by said system tag; and

    data consistency means for ensuring shared data consistency between the first and second data processing elements, the data consistency means including system bus monitoring means, coupled to the system bus, for monitoring I/O requests over the system bus.

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