Dual current data bus clamp circuit of semiconductor memory device

• US 5,091,886 A
• Filed: 05/28/1991
• Issued: 02/25/1992
• Est. Priority Date: 05/31/1990
• Status: Expired due to Term

• Current Assignee: Oki Semiconductor Company Limited (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Ishimura, Tamihiro, Ohtsuki, Yoshio, Miyawaki, Masahumi
• Primary Examiner(s): CLAWSON JR, JOSEPH
• Application Number:
  US07/706,206
• Time in Patent Office: 273 Days
• Field of Search: 365/189.06, 365/204, 365/207, 365/208, 365/233
• US Class Current: 365/204
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising

Abstract

A data bus clamping circuit for use in a semiconductor memory device includes a memory cell array for storing data, a row address decoder for decoding row address signals taken in by a row address strobe signal to select memory cells in a row direction of the memory cell array, a column address decoder for decoding column address signals based on a column address decoder enabling signal to select memory cells in a column direction of the memory cell array, complementary data buses for transmitting data read out from the memory cell array, a data bus pull-up circuit for pulling up the complementary data buses, and a differential amplification type of readout circuit for amplifying on a differential basis data on the complementary data buses to output readout data. The data bus clamping circuit includes a first discharge circuit for discharging electric charge on the complementary data buses during an active period of the row address strobe signal, and a second discharge circuit for discharging electric charge on the complementary data buses with a discharge ability larger than the first discharge circuit, during a period of time from the time the active period of the row address strobe signal starts until the column address decoder enabling signal becomes active.

Claims

1. In a semiconductor memory device comprising a memory cell array for storing data, a row address decoder for decoding row address signals taken in by a row address strobe signal to select memory cells in a row direction of the memory cell array, a column address decoder for decoding column address signals based on a column address decoder enabling signal to select memory cells in a column direction of the memory cell array, conplementary data buses for transmitting data read out from said memory cell array, a data bus pull-up circuit for pulling up said complementary data buses, a data bus clamping circuit for clamping said complementary data buses to a predetermined potential, and a differential amplification type of readout circuit for amplifying on a differential basis data on said complementary data buses to output readout data, said data bus clamping circuit comprising:

a first discharge circuit for discharging electric charge on said complementary data buses during an active period of the row address strobe signal; and

a second discharge circuit for discharging electric charge on said complementary data buses with a discharge ability larger than said first discharge circuit, during a period of time from the time the active period of the row address strobe signal starts until the column address decoder enabling signal becomes active.

2. A data bus clamping circuit according to claim 1 further comprising a control circuit for controlling an operation of the second discharge circuit by a clamp signal.

3. A data bus clamping circuit according to claim 1, wherein said first discharge circuit is proivded with first, second, third and fourth MOS transistors which are designed to provide small mutual conductance gm1, connected to one of said complementary data buses is a drain electrode of the first MOS transistor, of which a gate electrode is connected to the row address latch signal, a source electrode of the first MOS transistor is connected to drain and gate electrodes of the second MOS transistor, of which a source electrode is connected to the earth potential, connected to the other data bus is a drain electrode of the third MOS transistor, of which a gate electrode is connected to the row address latch signal, and a source electrode of the third MOS transistor is connected to drain and gate electrodes of the fourth MOS transistor, of which a source electrode is connected to the earth potential.

4. A data bus clamping circuit according to claim 1, wherein said second discharge circuit is provided with fifth, sixth, seventh and eighth MOS transistors which are adapted to provide relatively large mutual conductance gm2, connected to one of said complemntary data buses is a drain electrode of the fifth MOS transistor, of which a gate electrode is connected to a clamp signal and a gate electrode of the seventh MOS transistor, a source electrode of the fifth MOS transistor is connected to drain and gate electrodes of the sixth MOS transistor, of which a source electrode is connected to the earth potential, the source electrode of the fifth MOS transistor is also connected to drain and gate electrodes of the eighth MOS transistor, and connected to the other data bus is a drain electrode of the seventh MOS transistor, of which a source electrode is connected to the drain electrode of the eighth MOS transistor.

5. A data bus clamping circuit according to claim 1, wherein said first discharge circuit is provided with first, second, third and fourth MOS transistors which are adapted to provide small mutual conductance gm1, and said second discharge circuit is provided with fifth, sixth, seventh and eighth MOS transistors which are adapted to provide relatively large mutual conductance gm2, in which the mutual conductance gm1 of first, second, third and fourth MOS transistors in the first discharge circuit and the mutual conductance gm2 of fifth, sixth, seventh and eighth MOS transistors in the second discharge circuit are set to be approximately in the ratio 1:

10 to 20.

6. A data bus clamping circuit according to claim 2, wherein said semiconductor memory device includes a control signal generating circuit, and said control circuit comprises an invertor for entering a row address latch signal output form said control signal generating circuit, and an NOR gate for entering an output of said invertor and the column address decoder enabling signal and for outputting the clamp signal.

7. A data bus clamping circuit according to claim 6, wherein said second discharge circuit is provided with fifth, sixth, seventh and eighth MOS transistors which are adapted to provide relatively large mutual conductance gm2, connected to one of said complementary data buses is a drain electrode of the fifth MOS transistor, of which a gate electrode is connected to the clamp signal and a gate electrode of the seventh MOS transistor, a source electrode of the fifth MOS transistor is connected to drain and gate electrodes of the sixth MOS transistor, of which a source electrode is connected to the ground potential, the source electrode of the fifth MOS transistor is also connected to drain and gate electrodes of the eighth MOS transistor, and connected to the other data bus is a drain electrode of the seventh MOS transistor, of which a source electrode is connected to the drain electrode of eighth MOS transistor.

8. A data bus clamping circuit according to claim 5, wherein each of said MOS transistors is an N channel type of MOS transistor.

9. A data bus clamping circuit according to claim 7, wherein each of said MOS transistors is an N channel type of MOS transistor.

20. A device according to claim 4 wherein each of said MOS transistors is an N channel type of MOS transistor.

10. A semiconductor memory device comprising:

a memory cell array for storing data;

a row address decoder for decoding row address signals taken in by a row address strobe signal to select memory cells in a row direction of the memory cell array;

a column address decoder for decoding column address signals based on a column address decoder enabling signal to select memory cells in a column direction of the memory cell array;

complementary data buses for transmitting data read out from said memory cell array;

a data bus pull-up circuit for pulling up said complementary data buses;

a data bus clamping circuit for clamping said complementary data buses to a predetermined potential; and

a differential amplification type of readout circuit for amplifying on a differential basis data on said complementary data buses to output readout data,

said data bus clamping circuit comprising;

a first discharge circuit for discharging electric charge on said complementary data buses during an active period of the row address strobe signal; and

a second discharge circuit for discharging electric charge on said complemental data buses with a discharge ability larger than said first discharge circuit, during a period of time from the time the active period of the row address strobe signal starts until the column address decoder enabling signal becomes active.

11. A device according to claim 10, wherein data bus clamping circuit further comprises a control circuit for controlling an operation of the second discharge circuit by a clamp signal.

12. A device according to claim 10, wherein said first discharge circuit is provided with first, second, third and fourth MOS transistors which are adapted to provide small mutual conductance gm1, connected to one of said complemental data buses is a drain electrode of the first MOS transistor, of which a gate electrode is connected to the row address latch signal, a source electrode of the first MOS transistor is connected to drain and gate electrodes of the second MOS transistor, of which a source electrode is connected to the earth potential, connected to the other data bus is a drain electrode of the third MOS transistor, of which a gate electrode is connected to the row address latch signal, and a source electrode of the third MOS transistor is connected to drain and gate electrodes of the fourth MOS transistor, of which a source electrode is connected to the ground potential.

13. A device according to claim 10, wherein said second discharge circuit is provided with fifth, sixth, seventh and eighth MOS transistors which are adapted to provide relatively large mutual conductance gm2, connected to one of said complementary data buses is a drain electrode of the fifth MOS transistor, of which a gate electrode is connected to a clamp signal and a gate electrode of the seventh MOS transistor, a source electrode of the fifth MOS transistor is connected to drain and gate electrodes of the sixth MOS transistor, of which a source electrode is connected to the earth potential, the source electrode of the fifth MOS transistor is also connected to drain and gate electrodes of the eighth MOS transistor, and connected to the other data bus is a drain electrode of the seventh MOS transistor, of which a source electrode is connected to the drain electrode of the eighth MOS transistor.

14. A device according to claim 10, wherein said first discharge circuit is provided with first, second, third and fourth MOS transistors which are adapted to provide small mutual conductance gm1, and said second discharge circuit is provided with fifth, sixth, seventh and eighth MOS transistors which are adapted to provide relatively large mutual conductance gm2, in which the mutual conductance gm1 of first, second, third and fourth MOS transistors in the first discharge circuit and the mutual conductance gm2 of fifth, sixth, seventh and eighth MOS transistors in the second discharge circuit are set to be approximately in the ration 1:

10 to 20.

15. A device according to claim 11 further comprising a control signal generating circuit, wherein said control circuit comprises an invertor for entering a row address latch signal output from said control signal generating circuit, and an NOR gate for entering an output of said invertor and the column address decoder enabling signal and for outputting the clamp signal which are supplied to the gate electrode of the fifth MOS transistor and the gate electrode of the seventh MOS transistor.

16. A device according to claim 15, wherein said second discharge circuit is provided with fifth, sixth, seventh and eighth MOS transistors which are adapted to provide relatively large mutual conductance gm2, connected to one of said complementary data buses is a drain electrode of the fifth MOS transistor, of which a gate electrode is connected to the clamp signal and a gate electrode of the seventh MOS transistor, a source electrode of the fifth MOS transistor is connected to drain and gate electrodes of the sixth MOS transistor, of which a source electrode is connected to the ground potential, the source electrode of the fifth MOS transistor is also connected to drain and gate electrodes of the eighth MOS transistor, and connected to the other data bus is a drain electrode of the seventh MOS transistor, of which a source electrode is connected to the drain electrode of eighth MOS transistor.

17. A device according to claim 14, wherein each of said MOS transistors is an N channel type of MOS transistor.

18. A device according to claim 16, wherein each of said MOS transistors is an N channel type of MOS transistor.

19. A device according to claim 12 wherein each of said MOS transistors is an N channel type of MOS transistor.