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Integrated single structure branch prediction cache

  • US 5,093,778 A
  • Filed: 02/26/1990
  • Issued: 03/03/1992
  • Est. Priority Date: 02/26/1990
  • Status: Expired due to Term
First Claim
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1. An integrated branch prediction cache structure comprising:

  • a program counter content addressable memory (PcCAM) for storing branch instruction addresses;

    a valid bit (Vbit) memory associated with said PcCAM;

    a branch address cache (BAC) for storing branch target instruction addresses;

    a branch history cache (BHC) for storing data indicating the direction of past branches;

    a branch target cache (BTC) for storing instruction data at said branch target instruction addresses;

    a target instruction valid (TIV) memory associated with said BTC;

    each of said PcCAM, Vbit memory, BAC, BHC, BTC, and TIV memory containing N entries;

    each of said BAC, BHC, BTC, and TIV memory having N read select inputs, corresponding to its N entries, the appearance of an active signal at one of which allows the corresponding entry to be read;

    said PcCAM having associated means, responsive to an address input, for determining whether any entry corresponds to input, and for asserting a read select signal corresponding to any match of a specific PcCAM entry that corresponds to the address input;

    means for applying said read select signal to the read select input of each of said BAC, BHC, BTC, and TIV memory entries that correspond to the specific PcCAM entry to allow such corresponding entries to be read.

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