Integrated single structure branch prediction cache
First Claim
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1. An integrated branch prediction cache structure comprising:
- a program counter content addressable memory (PcCAM) for storing branch instruction addresses;
a valid bit (Vbit) memory associated with said PcCAM;
a branch address cache (BAC) for storing branch target instruction addresses;
a branch history cache (BHC) for storing data indicating the direction of past branches;
a branch target cache (BTC) for storing instruction data at said branch target instruction addresses;
a target instruction valid (TIV) memory associated with said BTC;
each of said PcCAM, Vbit memory, BAC, BHC, BTC, and TIV memory containing N entries;
each of said BAC, BHC, BTC, and TIV memory having N read select inputs, corresponding to its N entries, the appearance of an active signal at one of which allows the corresponding entry to be read;
said PcCAM having associated means, responsive to an address input, for determining whether any entry corresponds to input, and for asserting a read select signal corresponding to any match of a specific PcCAM entry that corresponds to the address input;
means for applying said read select signal to the read select input of each of said BAC, BHC, BTC, and TIV memory entries that correspond to the specific PcCAM entry to allow such corresponding entries to be read.
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Abstract
The present invention provides an improved branch prediction cache (BPC) structure that combines various separate structures into one integrated structure. In conjunction with doing this, the present invention is able to share significant portions of hardware cost and design complexity overhead. As a result, the cost-performance trade-off for implementing dynamic branch prediction for target address, branch direction, and target instructions aspects of branches shifts to where "full" branch prediction is now more practical.
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Citations
6 Claims
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1. An integrated branch prediction cache structure comprising:
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a program counter content addressable memory (PcCAM) for storing branch instruction addresses; a valid bit (Vbit) memory associated with said PcCAM; a branch address cache (BAC) for storing branch target instruction addresses; a branch history cache (BHC) for storing data indicating the direction of past branches; a branch target cache (BTC) for storing instruction data at said branch target instruction addresses; a target instruction valid (TIV) memory associated with said BTC; each of said PcCAM, Vbit memory, BAC, BHC, BTC, and TIV memory containing N entries; each of said BAC, BHC, BTC, and TIV memory having N read select inputs, corresponding to its N entries, the appearance of an active signal at one of which allows the corresponding entry to be read; said PcCAM having associated means, responsive to an address input, for determining whether any entry corresponds to input, and for asserting a read select signal corresponding to any match of a specific PcCAM entry that corresponds to the address input; means for applying said read select signal to the read select input of each of said BAC, BHC, BTC, and TIV memory entries that correspond to the specific PcCAM entry to allow such corresponding entries to be read. - View Dependent Claims (2, 3, 4, 5, 6)
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Specification