Trench pillar for wafer processing

• US 5,094,973 A
• Filed: 06/21/1990
• Issued: 03/10/1992
• Est. Priority Date: 11/23/1987
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Pang, Harry F.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Pham, Long
• Application Number:
  US07/541,676
• Time in Patent Office: 628 Days
• Field of Search: 437/67, 357/49, 357/55, 156/643, 156/644
• US Class Current: 438/424
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence

Abstract

A T-shaped trench intersection shaped to make uniform the wall-to-wall spacing at the trench intersection and prevent the formation of voids when the trench is filled with a conformal insulating material.

Claims

1. A method for forming an isolation trench structure in a semiconductor material, comprising the steps of:

forming a first trench intersecting with a second trench;

forming a pillar within said trench intersection to reduce the fillable volume within essentially said trench intersection; and

filling said trenches with a conformal insulating material.

2. The method claim 1 further including forming said intersection as a T-shaped trench structure.

3. The method of claim 2, further including forming said intersection with inside corners which are substantially rounded, and forming said T with a cusped trench sidewall which is rounded such that said wall-to-wall spacing of said intersection is uniform.

4. The method of claim 1, further including forming a trench matrix in a semiconductor wafer, and forming said trench matrix with a plurality of said uniform wall-to-wall intersections.

5. The method of claim 1, further including forming a circuit in each said semiconductor area.

6. The method of claim 3 further comprising the step of forming said intersection with inside corners which are substantially rounded.

7. The method of claim 1, further comprising the step of forming said intersection as a crossing intersection.

8. A method for forming an isolation structure in a semiconductor material, comprising the steps of:

forming a first trench intersecting with a second trench;

forming a pillar of material centrally within essentially said trench intersection; and

filling said trenches with a conformal insulating material.

9. The method of claim 8, wherein the wall-to-wall spacing at said intersections is substantially equal to the pillar width of said trenches.