Power MOSFET

• US 5,095,343 A
• Filed: 11/06/1990
• Issued: 03/10/1992
• Est. Priority Date: 06/14/1989
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Klodzinski, Stanley J., Ronan, Harold R. Jr., Neilson, John M. S., Wheatley, Carl F. Jr.
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Meier, Stephen D.
• Application Number:
  US07/609,054
• Time in Patent Office: 490 Days
• Field of Search: 357/23.4, 357/23.8, 357/20, 357/13
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A VDMOS device includes a wafer of semiconductor material having first and second opposed major surfaces. A drain region of a first conductivity type extends along the one major surface. A plurality of body regions of a second conductivity type is in the body region at the one major surface. Each body region forms with the drain region a body/drain PN junction, the intersection of which with the first major surface is in a closed path, preferably a hexagon. A plurality of spaced source regions of the one conductivity type are in each of the body regions with each source region being positioned opposite the space between two source regions in the adjacent body region. Each source region forms with the body region a source/body PN junction. A portion of each of the source/body PN junctions is adjacent to but spaced from its respective drain/body PN junction to form a channel region therebetween. An insulated gate is over the first major surface and the channel regions. The plurality of spaced channel regions in each of the body regions provides the device with improved surface operating area.

Claims

1. A VDMOS device comprising:

a semiconductor wafer having first and second opposing major surfaces;

a first conductivity type drain region at the first surface;

a plurality of second conductivity type body regions in the drain region at said first surface each forming with the drain region a body/drain PN junction the interface of which with the first surface extends in a closed path;

a plurality of spaced first conductivity type source regions in each body region and at said first surface, each source region forming with its body region a source/body PN junction at least a portion of which is adjacent but spaced from the body/drain PN junction of its respective body region with the drain region, the space along the body region between the adjacent portion of the body/drain PN junction of said body region and each of the source/drain PN junctions in said body region forming channel regions, the space between adjacent source regions in each body region being at least equal to the width of the portion of each of the source/body PN junctions which is adjacent the body/drain PN junction, and each of said source regions in a body region being positioned so as to be directly opposite the space between two source regions in an adjacent body region; and

an insulated gate electrode overlying the channel regions.

2. A device in accordance with claim 1 in which the intersection of each of the body/drain PN junction and said first major surface is in the form of a hexagon in the plane of said first surface, and each of the source/drain PN junctions in each drain region has a portion which extends along but is spaced from a side of the hexagon.

3. A device in accordance with claim 2 including only three source regions in each body region with the portions of the source/body PN junctions being along alternate sides of the hexagon.

4. A device in accordance with claim 3 in which the intersection of each of the source/drain PN junctions with the first surface is in the form of a truncated triangle with the base of the triangle being adjacent the body/source PN junction.

5. A device in accordance with claim 3 in which the drain region includes a high conductivity portion extending along the second major surface and a lower conductivity portion extending along the first major surface.

6. A device in accordance with claim 5 in which the body region has a high conductivity portion in the center thereof which is deeper into the wafer than the surrounding lower conductivity portion of the body region and the source regions extend around the higher conductivity portion of the drain region.

7. A device in accordance with claim 6 in which the insulated gate includes a layer of insulating material over the first major surface and the channel regions, and a conductive electrode layer over the insulating layer and extending over the channel regions.

8. A VDMOS device comprising:

a semiconductor wafer having first and second opposing major surfaces;

a first conductivity type drain region at the first surface;

a second conductivity type region at the second surface and having an interface with the drain region;

a plurality of second conductivity type body regions in the drain region at said first surface each forming with the drain region a body/drain PN junction the interface of which with the first surface extends in a closed path;

a plurality of spaced first conductivity type source regions in each body region and at said first surface, each source region forming with its respective body region a source/body PN junction at least a portion of which is adjacent but spaced from the body/drain PN junction of its respective body region along said first surface, the space along the body region between the adjacent portions of the body/drain PN junction and each of the source/drain junctions forming channel regions, the space between adjacent source regions in each body region being at least equal to the width of the portion of each source/body PN junctions which is adjacent the body/drain PN junction, each of said source regions in a body region being positioned directly opposite the space between two source regions in an adjacent body region; and

an insulated gate electrode overlying the channel regions.

9. A device in accordance with claim 8 in which the intersection of each body/drain PN junction and said first major surface is in the form of a hexagon along the plane of the first surface, and each of the source/drain PN junctions in each drain region has a portion which extends along but is spaced from a side of the hexagon.

10. A device in accordance with claim 9 including only three source regions in each body region with the portion of each source/body PN junction being positioned along alternate sides of the hexagon.

11. A device in accordance with claim 10 in which each of the intersections of each source/drain PN junction with the first surface is in the form of a truncated triangle with the base of the triangle being adjacent the body/drain PN junction.

12. A device in accordance with claim 11 in which the insulated gate includes a layer of insulating material over the first surface and the channel regions, and a conductive electrode layer over the insulating layer and extending over the channel regions.

13. A device in accordance with claim 12 in which the drain region includes a high conductivity portion along the interface with the second conductivity region which is at the second surface, and a lower conductivity portion along the first major surface.