Highly compact EPROM and flash EEPROM devices

• US 5,095,344 A
• Filed: 06/08/1988
• Issued: 03/10/1992
• Est. Priority Date: 06/08/1988
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Eliyahou Harari
• Inventors: Harari, Eliyahou
• Primary Examiner(s): NGUYEN, VIET Q
• Assistant Examiner(s): Kim, Daniel
• Application Number:
  US07/204,175
• Time in Patent Office: 1,371 Days
• Field of Search: 357/23.5, 357/23.1, 357/23.3, 357/23.4, 357/41, 357/53, 357/45
• US Class Current: 257/328
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5613 Multilevel memory cell with additional gates, not being floating or control gates
• CPC Class Codes: G11C 2211/5631 Concurrent multilevel reading of more than one cell
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 2211/5644 Multilevel memory comprising counting devices
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/82 for EEPROMs
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 41/00 Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
• CPC Class Codes: H10B 41/10 characterised by the top-view layout
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.

Claims

1. A flash electrically erasable and programmable read only memory cell, comprising:

a semiconductor substrate containing a source region and a drain region spaced apart in a first direction across a surface thereof with a channel region therebetween,

a floating gate positioned at least partially over but insulated from said channel region, said floating gate having a first predetermined dimension between opposing edges thereof in a second direction across said substrate surface that is substantially perpendicular to said first direction, said opposing edges being positioned outside said channel region on opposite sides thereof,

a control gate positioned adjacent to but insulated from the floating gate and the semiconductor substrate,

a pair of erase gates spaced apart in said second direction by a second predetermined dimension which is less than said first predetermined dimension and oriented to extend a part way across the floating gate from its said opposing edges, thereby to form tunnel erase regions of overlap between the floating gate and the pair of erase gates, and

a dielectric positioned between said floating gate and said pair of erase gates in said tunnel erase regions of overlap, said dielectric being positioned in contact with opposing surfaces of said floating and erase gates and characterized by allowing electrical charge to tunnel between then,

whereby a total area of said tunnel erase regions of overlap is determined by the difference between said first and second predetermined dimensions and is insensitive to misalignment between the floating gate and the pair of erase gates in said second direction.

2. The memory cell according to claim 1 wherein said pair of erase gates are positioned on a top surface of said floating gate facing away from said substrate.

3. A flash electrically erasable and programmable read only memory cell, comprising:

a semiconductor substrate containing source and drain regions elongated in a first direction across a surface thereof and separated in a second direction across said substrate surface by a channel region, said first and second directions being substantially perpendicular to each other,

a floating gate positioned at least partially over but insulated from said channel region, said floating gate having a predetermined dimension between substantially parallel opposing edges thereof in said first direction,

a pair of erase gates having substantially parallel opposing edges spaced apart a distance in said first direction that is less than said predetermined dimension and oriented to extend a part way across the floating gate from its said opposing edges, thereby to form regions of overlap between the floating gate opposing edges and the pair of erase gate opposing edge with a total area determined by the difference between said predetermined floating gate dimension and said erase gate spacing distance,

a tunnel dielectric positioned between opposing surfaces of said floating gate and said pair of erase gates substantially throughout the regions of overlap between them, and

a control gate positioned adjacent to but insulated from said pair of erase gates and also overlying said floating gate,

whereby a total area of overlap between the floating and erase gates is insensitive to misalignment therebetween in said first direction.

4. The memory cell according to claim 3 wherein said floating gate extends in said second direction over only a portion of the channel region adjacent to said drain region, and further wherein said control gate is positioned over another portion of the channel region adjacent to said source region and separated from said substrate by a thin gate dielectric.

5. The memory cell according to claim 3 wherein said pair of erase gates extend in said second direction between said source and drain regions and are located close to said substrate with a gate dielectric therebetween, thereby forming field plates that electrically isolate said channel region and adjacent portions of said substrate in said first direction.

6. A flash electrically erasable and programmable read only memory cell, comprising:

a semiconductor substrate containing a source region and a drain region extending in a first direction across a surface thereof and being separated in a second direction across said substrate surface by a channel region, said first and second directions being substantially perpendicular to each other,

a floating gate extending at least partially across said substrate channel region in said second direction but insulated therefrom and having sidewalls at opposite edges thereof in said first direction which are located outside of said channel region,

a control gate positioned over but insulated from the floating gate and the semiconductor substrate,

a pair of erase gates extending in said second direction between said source and drain regions and positioned along said opposite edges of said floating gate and adjacent to sidewalls thereof, and

a tunnel dielectric extending between at least one of the floating gate sidewalls and its adjacent erase gate.

7. The memory cell according to claim 6 wherein said floating gate extends across only a portion of the channel region in said second direction adjacent to said drain region, and further wherein said control gate is positioned over another portion of the channel region adjacent to said source region and separated from said substrate by a thin gate dielectric.

8. The memory cell according to claim 6 wherein said pair of erase gates are located close to said substrate with a gate dielectric therebetween, thereby forming field plates that electrically isolate between said channel region and adjacent portions of said substrate in said first direction.

9. The memory cell according to claim 6 wherein each of said sidewalls of said floating gate contains asperites, thereby to enhance an electron injection efficiency of said sidewalls.

10. The memory cell according to claim 6 wherein each of said opposing edges of said floating gate is formed into a sharp tip by virtue of the gate being sufficiently thin, thereby to enhance the electron injection efficiency of said sidewalls.

11. A flash electrically erasable and programmable read only memory cell, comprising:

a semiconductor substrate containing a source region and a drain region extending in a first direction across a surface thereof and being separated in a second direction across said substrate surface by a channel region, said first and second directions being substantially perpendicular to each other,

a floating gate extending at least partially across said substrate channel region in said second direction but insulated therefrom,

a control gate positioned over but insulated from the floating gate and the semiconductor substrate,

a pair of erase gates positioned on opposite sides of said floating gate in said first direction and extending across said channel in a second direction between said source and drain regions, at least one erase gate and the floating gate having capacitive coupling therebetween, and

a thin gate dielectric separating each of said pair of erase gates from the channel region of the substrate, thereby to provide electrical isolation of the memory cell in said first direction.

12. A flash electrically erasable and programmable read only memory cell, comprising:

a semiconductor substrate containing a source region and a drain region in a surface thereof and separated across said surface by a channel region,

a floating gate positioned at least partially over but insulated from said channel region, said floating gate having a given dimension between opposing edges thereof in a direction perpendicular to a direction between said source and drain regions,

a control gate extending across but insulated from said floating gate, said control gate having a dimension in a direction extending between said floating gate opposing edges that is less than said given dimension, thereby causing a top surface segment of the floating gate adjacent at least one of said opposing edges to be positioned outside of said control gate,

a tunnel dielectric layer carried by at least a portion of said floating gate top surface segment, and

an erase gate extending across said tunnel dielectric layer and insulated from said control gate in a manner to capacitively couple the erase gate with the floating gate in a tunnel erase region having an area that is insensitive to misalignment between said erase gate and said floating gate.

13. The memory cell according to claim 12 wherein said floating gate is positioned over only a portion of the channel region adjacent to said drain region, and further wherein said control gate extends over another portion of the channel region adjacent to said source region and is separated therefrom by a thin gate dielectric.

14. A flash electrically erasable and programmable read only memory cell, comprising:

a semiconductor substrate containing substantially parallel source and drain regions elongated in a first direction across a surface of said substrate and separated in a second direction across said substrate surface by a channel region, said first and second directions being substantially perpendicular to each other,

a floating gate formed of a first electrically conductive layer and positioned at least partially across but insulated from said channel region, said floating gate having a predetermined dimension thereacross in said first direction between substantially parallel opposing edges thereof,

a pair of erase gates having opposing edges substantially parallel with said floating gate opposing edges and spaced apart a distance in said first direction that is less than said predetermined dimension and oriented to extend a part way across the floating gate from each of its said opposing edges, said erase gates being formed in a second electrically conductive layer and extending in the second direction between the source and drain regions,

a layer of tunnel dielectric positioned inbetween said floating gate and said erase gates in at least a portion of an area of overlap therebetween, and

a control gate extending in said second direction across and insulated from said floating gate inbetween said pair of erase gates, said control gate being formed of a third electrically conductive layer and being insulated from said erase gates.

15. The memory cell according to claim 14 wherein said layer of tunnel dielectric extends substantially entirely across an area of overlap between the floating gate and the erase gate.