Method and apparatus for verifying timing during simulation of digital circuits

• US 5,095,454 A
• Filed: 05/25/1989
• Issued: 03/10/1992
• Est. Priority Date: 05/25/1989
• Status: Expired due to Term

• Current Assignee: Gateway Design Automation Corporation
• Original Assignee: Gateway Design Automation Corporation
• Inventors: Huang, Chi-Lai
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Ramirez, Ellis B.
• Application Number:
  US07/357,076
• Time in Patent Office: 1,020 Days
• Field of Search: 364/578, 364/488, 364/489, 364/490, 364/569, 371/23
• US Class Current: 703/19
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test
• CPC Class Codes: G06F 30/3312 Timing analysis

Abstract

A digital circuit simulation method and apparatus provide for critical path timing analysis of digital circuitry using a hybrid path tracing method. The hybrid path tracing performs path tracing when, for example, simulation values change at designated inputs. The path tracing can employ the simulation values for eliminating blocked paths. During tracing, the method and apparatus determine the shortest and longest paths from each input or beginning point to each end point. The end points are typically storage elements such as latches, flip-flops or systems outputs at a high functional level. The critical path tracing analysis finds the shortest and longest paths from the beginning point to the end point and records and saves the violation history, if any, associated with those paths. A timing template allows the user to develop the necessary input stimuli, in a logical ordered format to test the timing behavior of the digital circuit to be designed. Special procedures are also available for enabling the iteration of stimuli to check the timing of a transparent latch-based design. The system thus provides as an output either a summary or detailed history of violations at selected levels within the circuit to be analyzed. User input enables the system to isolate upon particular portions of the circuitry for determining correct operation.

Claims

1. A method for performing a timing analysis simulation upon a digital circuit design comprising the steps of

inputting said digital circuit design to an analysis apparatus,

simulating a logical function evaluation of said design for each of successive simulation time instants,

performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs, and

eliminating paths subject to said path tracing analysis depending upon the signal value results of said simulation step at said designated inputs.

2. The method of claim 1 further comprising the step of

performing a timing analysis of said digital circuit design using a hybrid path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs whenever the value of signals at said designated inputs varies as a result of said simulating step.

3. The method of claim 1 further wherein

said performing step comprises

determining a shortest and a longest delay path between said designated inputs and end points of said paths, and

saving the violation history of only the two paths representing the longest and shortest paths from a designated input to a said end point.

4. The method of claim 1 further comprising the steps of

inputting a user specified timing template to said apparatus, and

setting input stimuli with regard to at least one of said designated inputs in accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested.

5. The method of claim 1 further comprising the step of

providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing at least one transparent latch.

6. A method for performing a timing analysis simulation upon a digital circuit design comprising the steps of

inputting a user specified timing template,

simulating a logical function evaluation of said design for each successive simulation time instance,

performing a timing analysis of said digital circuit design using a hybrid path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs whenever the value of signals at said designated inputs varies as a result of said simulating step, and

outputting the results of said time analysis for display to an end user.

7. The method of claim 6 further wherein said performing step comprises

determining a shortest and a longest delay path between said designated inputs and end points of said paths, and

saving the violation history of only the two paths representing the longest and shortest paths from a designated input to a said end point.

8. The method of claim 6 further comprising the steps of

inputting a user specified timing template to said apparatus, and

setting the input stimuli with regard to at least one of said designated inputs in accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested.

9. The method of claim 6 further comprising the step of

providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing at least one transparent latch.

10. A method for performing a timing analysis simulation upon a digital circuit design comprising the steps of

inputting said digital circuit design to an analysis system,

simulating a logical function evaluation of said design for each of successive simulation time instants,

performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said inputs, said performing step comprising,

determining a shortest and a longest delay path between said designated inputs and end points of said paths, and

saving the timing violation history of only the two paths representing the longest and shortest paths from a designated input to a said end point, and

displaying the timing violation history of the saved paths to an end user.

11. The method of claim 10 further comprising the steps of

inputting a user specified timing template to said apparatus, and

setting the input stimuli with regard to at least one of said designated inputs in accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested.

12. The method of claim 10 further comprising the steps of

providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing at least one transparent latch.

13. A method for performing a timing analysis simulation upon a digital circuit design comprising the steps of

inputting said digital circuit design to an analysis apparatus,

inputting a user specified timing template to said apparatus,

simulating a logical function evaluation of said design for each of successive simulation time instants,

performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said inputs,

setting the input stimuli with regard to at least one of said designated inputs in accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested, and

displaying the timing violation history of paths as a result of said timing analysis of said digital circuit design.

14. The method of claim 13 further comprising the step of

providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing at least one transparent latch.

15. A method for performing a timing analysis simulation upon a digital circuit design comprising the steps of

inputting the digital circuit design to an analysis apparatus,

simulating a logical function evaluation of said design for each of successive simulation time instants,

performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths starting at said designated inputs,

providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing at least one transparent latch, and

displaying to an end user a timing violation history for said digital circuit design.

16. A method for performing a timing analysis simulation upon a digital circuit design comprising the steps of

inputting said digital circuit design to an analysis apparatus,

simulating a logical function evaluation of said design for each of successive simulation time instants,

performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs,

eliminating paths subject to said path tracing analysis depending upon the signal value results of said simulation step at said designated inputs,

said performing step comprising

determining a shortest and a longest delay path between said designated inputs and end points of said paths, and

saving the timing violation history of only the two paths representing the longest and shortest paths from a designated input to a said end point,

performing a timing analysis of said digital circuit design using a hybrid path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs whenever the value of signals at said designated inputs varies as a result of said simulating step,

inputting a user specified timing template to said apparatus,

setting the input stimuli with regard to at least one of said designated inputs in accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested,

providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing at least one transparent latch, and

displaying to an end user a timing violation history for said digital circuit design.

17. Apparatus for performing a timing analysis simulation upon a digital circuit design comprising

means for inputting said digital circuit design to an analysis apparatus,

means for simulating a logical function evaluation of said design for each of successive simulation time instants,

means for performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs, and

means for eliminating paths subject to said path tracing analysis depending upon the signal value results of said simulation step at said designated inputs.

18. Apparatus according to claim 17 further comprising

means for performing a timing analysis of said digital circuit design using a hybrid path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs whenever the value of signals at said designated inputs varies as a result of said simulating step.

19. Apparatus according to claim 17 wherein

said performing means comprises

means for determining a shortest and a longest delay path between said designated inputs and end points of said paths, and

means for saving the violation history of only the two paths representing the longest and shortest paths from a designated input to a said end point.

20. Apparatus according to claim 17 further comprising

means for inputting a user specified timing template, and

means for setting the input stimuli with regard to at least one of said designated inputs in accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested.

21. Apparatus according to claim 17 further comprising

means for providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing transparent latches.

22. Apparatus for performing a timing analysis simulation upon a digital circuit design comprising

means for inputting said digital circuit design to an analysis apparatus,

means for simulating a logical function evaluation of said design for each successive simulation time instance,

means for performing a timing analysis of said digital circuit design using a hybrid path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs whenever the value of signals at said designated inputs varies as a result of said simulating step, and

means for outputting the results of said time analysis for display to an end user.

23. Apparatus according to claim 22 wherein

said performing means comprises

means for determining a shortest and a longest delay path between said designated inputs and end points of said paths, and

means for saving the violation history of only the two paths representing the longest and shortest paths from a designated input to a said end point.

24. Apparatus according to claim 22 further comprising

means for inputting a user specified timing template, and

means for setting the input stimuli with regard to at least one of said designated inputs in accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested.

25. Apparatus according to claim 22 further comprising

means for providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing transparent latches.

26. Apparatus for performing a timing analysis simulation upon a digital circuit design comprising

means for inputting said digital circuit design to the analysis apparatus,

means for simulating a logical function evaluation of said design for each of successive simulation time instants,

means for performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs, said performing means comprising

means for determining a shortest and a longest delay path between said designated inputs and end points of said paths, and

means for saving the timing violation history of only the two paths representing the longest and shortest paths from a designated input to a said end point, and

means or displaying the timing violation history of the saved paths to an end user.

27. Apparatus according to claim 26 further comprising

means for inputting a user specified timing template, and

means for setting the input stimuli with regard to at least one of said designated inputs in accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested.

28. Apparatus according to claim 26 further comprising

means for providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing transparent latches.

29. Apparatus for performing a timing analysis simulation upon a digital circuit design comprising

means for inputting said digital circuit design to said apparatus,

means for inputting a user specified timing template,

means for simulating a logical function evaluation of said design for each of successive simulation time instants,

means for performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs,

means for setting the input stimuli with regard to at least one of said designated inputs in accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested, and

means for displaying the timing violation history of paths as a result of said timing analysis of said digital circuit design.

30. Apparatus according to claim 29 further comprising

means for providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing transparent latches.

31. Apparatus for performing a timing analysis simulation upon a digital circuit design comprising

means for inputting the digital circuit design to said apparatus,

means for simulating a logical function evaluation of said design for each of successive simulation time instants,

means for performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths starting at said designated inputs,

means for providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing transparent latches, and

means for displaying to an end user a timing violation history for said digital circuit design.

32. Apparatus for performing a timing analysis simulation upon a digital circuit design comprising

means for inputting said digital circuit design to an analysis apparatus,

means for simulating a logical function evaluation of said design for each of successive simulation time instants,

means for performing a timing analysis of said digital circuit design using a path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs,

means for eliminating paths subject to said path tracing analysis depending upon the signal value results of said simulation step at said designated inputs,

said performing means comprising

means for determining a shortest and a longest delay path between said designated inputs and end points of said paths, and

means for saving the timing violation history of only the two paths representing the longest and shortest paths from a designated input to a said end point,

means for performing a timing analysis of said digital circuit design using a hybrid path tracing analysis of said design from designated inputs to end points of signal propagation paths beginning at said designated inputs whenever the value of signals at said designated inputs varies as a result of said simulating step,

means for inputting a user specified timing template,

means for setting the input stimuli with regard to at least one of said designated inputs n accordance with said user specified timing template for determining the timing behavior of the digital circuit to be tested,

means for providing for iteration of stimuli at designated inputs for checking the timing of a digital circuit design having a loop containing transparent latches, and

means for displaying to an end user a timing violation history for said digital circuit design.