Method of making plastic encapsulated multichip hybrid integrated circuits

• US 5,096,852 A
• Filed: 02/07/1990
• Issued: 03/17/1992
• Est. Priority Date: 06/02/1988
• Status: Expired due to Term

• Current Assignee: Burr-Brown Corporation (Texas Instruments, Inc.)
• Original Assignee: Burr-Brown Corporation (Texas Instruments, Inc.)
• Inventors: Hobson, Larry D.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Graybill, David E.
• Application Number:
  US07/476,511
• Time in Patent Office: 769 Days
• Field of Search: 437/206, 437/220, 437/207
• US Class Current: 29/827
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45014 Ribbon connectors, e.g. rectangular cross-section
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H01L 23/49531 the additional leads being a wiring board
• CPC Class Codes: H01L 23/49575 Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: Y10T 29/49121 : Beam lead frame or beam lead device

Abstract

A method of making a hybrid integrated circuit includes bonding an insulative film to a first area of a lead frame flag, a second area of the lead frame flag being exposed. A plurality of individual metalized strips and a first flag area are formed on the film. A first integrated circuit chip such as a low power MOS chip, is bonded to the first flag area, and a second integrated circuit chip, such as a high power bipolar chip, is bonded to the second area of the lead frame flag. Bonding wires are bonded to connect various bonding pads and fingers of the lead frame of the two integrated circuit chips to various metallized strips on the insulative film. The chips, bonding wires, lead frame flag, lead frame fingers, and insulative film are encapsulated in plastic by transfer molding.

Claims

1. A method of making a hybrid integrated circuit, comprising the steps of:

(a) forming a metal layer pattern on a surface of an insulative film, the metal layer pattern including a plurality of individual bonding strips, a flag area, and a plating bus connected to the bonding strips and the flag area;

(b) electroplating a metal coating onto the metal layer pattern while applying an electroplating voltage to the plating bus;

(c) punching a piece out of the insulative film so as to produce a cutout larger than a first integrated circuit chip and so that the piece contains the bonding strips and the flag area and no interconnected parts of the plating bus are on the piece;

(d) attaching the piece to a first area of a flag of a lead frame to partially cover the flag of the lead frame while leaving uncovered a second area of the flag of the lead frame, the second area being exposed through the cutout, the lead frame having a plurality of fingers;

(e) die bonding the first integrated circuit chip to the second area of the flag of the lead frame, and die bonding a second integrated circuit to the flag area;

(f) wire bonding each of a plurality of bonding pads of the first and second integrated circuit chips to various bonding strips, respectively, and wire bonding some of the bonding strips to various fingers of the lead frame, respectively, and wire bonding each of the bonding strips located along an edge of the cutout to both a bonding pad on the first integrated circuit chip and to a corresponding bonding pad on the second integrated circuit chip, respectively, the first integrated circuit being a relatively high power dissipation integrated circuit, and the second integrated circuit being a relatively low power dissipation integrated circuit; and

(g) filling a volume containing the bonding wires, the first and second integrated circuit chips, and the flag and fingers of the lead frame with plastic to plastic-encapsulate the hybrid integrated circuit.

2. A method of making a hybrid integrated circuit, comprising the steps of:

(a) forming a metal layer pattern on a surface of an insulative film, the metal layer pattern including a plurality of individual bonding strips, a flag area, and a plating bus connected to the bonding strips and the flag area, the insulative film being in the form of an elongated ribbon having therein first and second groups of sprocket receiving holes located along opposed edges of portions of the insulative film, respectively;

(b) electroplating a metal coating onto the metal layer pattern while applying an electroplating voltage to the plating bus;

(c) punching a piece out of the insulative film so as to produce a cutout larger than a first integrated circuit chip and so that the piece contains the bonding strips and the flag area and no interconnected parts of the plating bus are on the piece;

(d) advancing the insulative film by means of a sprocketed spool and the sprocket receiving holes to align a portion of the insulative film with a punch;

(e) attaching the piece to a first area of a flag of a lead frame to partially cover the flag of the lead frame while leaving uncovered a second area of the flag of the lead frame, the second area being exposed through the cutout, the lead frame having a plurality of fingers;

(f) die bonding the first integrated circuit chip to the second area of the flag of the lead frame, and die bonding a second integrated circuit to the flag area;

(g) wire bonding each of a plurality of bonding pads of the first and second integrated circuit chips to various bonding strips, respectively, and wire bonding some of the bonding strips to various fingers of the lead frame, respectively, and wire bonding each of the bonding strips located along an edge of the cutout to both a bonding pad on the first integrated circuit chip and to a corresponding bonding pad on the second integrated circuit chip, respectively, the first integrated circuit being a relatively high power dissipation integrated circuit, and the second integrated circuit being a relatively low power dissipation integrated circuit; and

(h) filling a volume containing the bonding wires, the first integrated circuit chip, and the flag and fingers of the lead frame with plastic to plastic-encapsulate the hybrid integrated circuit.