Operation control circuit with secret code comparing means for remote control keypad

• US 5,097,260 A
• Filed: 08/21/1989
• Issued: 03/17/1992
• Est. Priority Date: 12/01/1988
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Ahn, Yun-soon
• Primary Examiner(s): Yusko, Donald J.
• Assistant Examiner(s): Magistre, Dervis
• Application Number:
  US07/396,107
• Time in Patent Office: 939 Days
• Field of Search: 340/825.3, 340/825.34, 340/825.56, 340/825.31, 340/825.69, 340/825.72, 358/194.1, 358/188, 358/349, 455/181, 455/352, 455/353, 235/382.5, 235/487, 359/142, 359/146
• US Class Current: 340/5.51
• CPC Class Codes: G07C 9/33 by means of a password
• CPC Class Codes: H03J 1/0025 in a remote control unit remote control tuning in general H03J9/00
• CPC Class Codes: H03J 2200/23 Remote control device with display showing data to be transmitted to the controlled apparatus

Abstract

An operation control circuit for a remote control keypad having a key operating section, a microcomputer and an oscillator is disclosed which comprises a key operating section, a display means, a secret code comparing means, and a gating means. The device of the present invention is characterized in that the users who are not informed of the secret codes are not allowed to use the device, or are allowed only limited uses of the device, thereby assuring the security of the remote controlled apparatus. There is a further advantage that, without observing the display means to confirm the operation state of the apparatus, the remote control can be carried out only by manipulating the keypad.

Claims

1. An operation control circuit for a remote control keypad having a key operating section, a microcomputer for outputting operation signals in accordance with the operation of said key operating section and an oscillator for supplying reference clocks to the microcomputer, for use with an audio and video apparatus, said operation control circuit comprising:

means for receiving the operational signals;

display means coupled to said receiving means, for decoding said operation signals of said microcomputer, and for displaying said operation signals in a visual display;

secret code comparing means coupled to said receiving means, for setting secret codes received from the key operating section and the microcomputer via said receiving means, and for comparing incoming codes received through said key operating section and the microcomputer with said secret codes; and

gating means coupled to said secret code comparing means, for transmitting operation signals of said microcomputer to a remote control signal receiver of the audio and video apparatus when said incoming codes and said secret codes are found to correspond to each other by said secret code comparing means.

2. The operation control circuit for a remote control keypad as claimed in claim 1, wherein:

said receiving means comprises first register means for storing the operation signals output from the microcomputer in accordance with manipulations by a user of the keys of a key operating section; and

said secret code comparing means comprises;

setting register means for storing the secret codes;

read register means for storing the incoming codes; and

comparator means for performing comparisons to check correspondence between the secret codes and the incoming codes from said setting register means and said read register means.

3. The operation control circuit for a remote control keypad as claimed in claim 1, wherein

said receiver means comprises first register means for storing the operation signals outputted from the microcomputer in accordance with manipulations by a user of the keys of the key operating section;

and

said display means comprises;

decoder means for decoding operation signals stored in the first register means; and

means for displaying the decoded operation signals in the form of recognizable letters.

4. The operation control circuit for a remote control keypad as claimed in claim 2, wherein said display means comprises:

decoder means for decoding operation signals stored in the first register means; and

means for displaying the decoded operation signals in the form of recognizable letters.

5. The operation control circuit of claim 1, wherein said gating means comprises:

first logic means having a first input port coupled for receiving code setting signals from the key operating section and a second input port coupled to a first node to receive comparison signals from said comparing means;

second logic means having a first input port coupled to receive said operational signals and a second input port coupled to said first node; and

third logic means having a first input port coupled to receive code reading signals from the key operating section and a second input port coupled to said first node.

6. The operation control circuit of claim 2, wherein said gating means comprises:

first logic means having a first input port coupled for receiving code setting signals from the key operating section and a second input port coupled to a first node to receive comparison signals from said comparator means;

second logic means having a first input port coupled to receive said operational signals and a second input port coupled to said first node; and

third logic means having a first input port coupled to receive code reading signals from the key operating section and a second input port coupled to said first node.

7. The operation control circuit of claim 3, wherein said gating means comprises:

first logic means having a first input port coupled for receiving code setting signals from the key operating section and a second input port coupled to a first node to receive comparison signals from said comparing means;

second logic means having a first input port coupled to receive said operational signals and a second input port coupled to said first node; and

third logic means having a first input port coupled to receive code reading signals from the key operating section and a second input port coupled to said first node.

8. The operation control circuit of claim 4, wherein said gating means comprises:

first logic means having a first input port coupled for receiving code setting signals from the key operating section and a second input port coupled to a first node to receive comparison signals from said comparing means;

second logic means having a first input port coupled to receive said operational signals and a second input port coupled to said first node; and

third logic means having a first input port coupled to receive code reading signals from the key operating section and a second input port coupled to said first node.

9. The operation control circuit of claim 1, wherein said gating means comprises:

first logic means providing a first input port coupled for receiving code setting signals from the key operating section and a second input port coupled to a first node to receive comparison signals from said secret code comparing means, for applying first logic signals to said comparing means in dependence upon said code setting signals and said comparison signals;

second logic means providing a third input port coupled to receive said operational signals and a fourth input port coupled to said first node, for generating output signals in dependence upon said operational signals and said comparison signals; and

third logic means providing a fifth input port coupled to receive code reading signals from the key operating section and a sixth input port coupled to said first node, for applying second logic signals to said secret code comparing means in dependence upon said code reading signals and said comparison signals.

10. The operation control circuit of claim 2, wherein said gating means comprises:

first logic means providing a first input port coupled for receiving code setting signals from the key operating section and a second input port coupled to a first node to receive comparison signals from said comparator means, for applying first logic signals to said setting register means in dependence upon said code setting signals and said comparison signals;

second logic means providing a third input port coupled to receive said operational signals and a fourth input port coupled to said first node, for generating output signals in dependence upon said operational signals and said comparison signals; and

third logic means providing a fifth input port coupled to receive code reading signals from the key operating section and a sixth input port coupled to said first node, for applying second logic signals to said read register means and to said first node in dependence upon said code reading signals and said comparison signals.

11. The operation control circuit of claim 3, wherein said gating means comprises:

first logic means providing a first input port coupled for receiving code setting signals from the key operating section and a second input port coupled to a first node to receive comparison signals from said secret code comparing means, for applying first logic signals to said secret code comparing means in dependence upon said code setting signals and said comparison signals;

second logic means providing a third input port coupled to receive said operational signals and a fourth input port coupled to said first node, for generating output signals in dependence upon said operational signals and said comparison signals; and

third logic means providing a fifth input port coupled to receive code reading signals from the key operating section and a sixth input port coupled to said first node, for applying second logic signals to said secret code comparing means in dependence upon said code reading signals and said comparison signals.

12. The operation control circuit of claim 4, wherein said gating means comprises:

first logic means providing a first input port coupled for receiving code setting signals from the key operating section and a second input port coupled to a first node to receive comparison signals from said comparator means, for applying first logic signals to said setting register means in dependence upon said code setting signals and said comparison signals;

second logic means providing a third input port coupled to receive said operational signals and a fourth input port coupled to said first node, for generating output signals in dependence upon said operational signals and said comparison signals; and

third logic means providing a fifth input port coupled to receive code reading signals from the key operating section and a sixth input port coupled to said first node, for applying second logic signals to said read register means and to said first node in dependence upon said code reading signals and said comparison signals.

13. The operation control circuit of claim 2, wherein said gating means receives code setting and code reading signals from the key operating section, comparison signals from said comparator means, and said operational signals from the microcomputer, applies first logic signals to said setting register means in dependence upon said code setting signals and said comparison signals, generates output signals in dependence upon said operational signals and said comparison signals, and applies second logic signals to said read register means in dependence upon said code reading signals and said comparison signals.

14. The operation control circuit of claim 4, wherein said gating means receives code setting and code reading signals from the key operating section, comparison signals from said comparator means, and said operational signals from the microcomputer, applies first logic signals to said setting register means in dependence upon said code setting signals and said comparison signals, generates output signals in dependence upon said operational signal and said comparison signals, and applies second logic signals to said read register means in dependence upon said code reading signals and said comparison signals.

15. In a remote control circuit having a keypad and a microcomputer coupled to generate operation signals in response to input signals from the keypad, an operational control circuit comprising:

first logic means providing a first input port coupled for receiving code setting signals from said keypad and a second input port coupled to a first node to receive comparison signals, for generating first logic signals at a first output port in dependence upon said code setting signals and said comparison signals;

second logic means providing a third input port coupled to receive the operation signals and a fourth input port coupled to said first node, for generating control signals at a second output port in dependence upon said operation signals and said comparison signals;

third logic means having a third output port coupled to said first node, and providing a fifth input port coupled to receive code reading signals from the keypad and a sixth input port coupled to said first node, for generating second logic signals at said third output port in dependence upon said code reading signals and said comparison signals;

first register means for storing the operation signals from the microcomputer in accordance with manipulations by a user of the keys of said keypad;

setting register means for storing, under control of said first logic signals, secret codes included among incoming code signals received from the keypad;

read register means coupled to receive said second logic signals, for storing the incoming code signals received from the keypad via said first register means;

comparator means for generating said comparison signals at said first node after performing comparisons between the secret codes and the incoming code signals stored by said respective setting register means and read register means;

decoder means for decoding operation signals stored in the first register means; and

display means coupled to said decoder means, for displaying decoded operation signals in the form of recognizable

16. A remote control circuit, comprising:

a keypad;

a microcomputer coupled to generate operation signals in response to input signals from the keypad;

first logic means providing a first input port coupled for receiving code setting signals from said keypad and a second input port coupled to a first node to receive comparison signals, for generating first logic signals at a first output port in response to coincidence between logic states of said code setting signals and said comparison signals;

second logic means providing a third input port coupled to receive the operation signals and a fourth input port coupled to said first node, for generating control signals at a second output port in response to coincidence between logic states of said operation signals and said comparison signals;

third logic means having a third output port coupled to said first node, and providing a fifth input port coupled to receive code reading signals from the keypad and a sixth input port coupled to said first node, for generating second logic signals at said third output port in response to coincidence between logic states of said code reading signals and said comparison signals;

first register means for storing operation signals from the microcomputer in accordance with manipulations by a user of the keys of said keypad;

setting register means for storing, under control of said first logic signals, secret code signals included among input signals received from said keypad via said first register means;

read register means coupled to receive said second logic signals, for storing incoming code signals included among said input signals received from said keypad via said first register means;

comparator means for generating said comparison signals after performing comparisons to check correspondence between the stored secret code signals and the stored incoming code signals;

a first diode coupled to transmit said comparison signals to said first node;

a second diode coupled to transmit said second logic signals between said third output port and said first node;

decoder means for decoding said operation signals stored in the first register means; and

display means coupled to said decoder means, for displaying decoded operation signals in the form of recognizable symbols.