Non-volatile memory structure
First Claim
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1. A non-volatile semiconductor memory system comprising:
- a volatile memory circuit for storing binary information in static form;
voltage level shifter means for elevating the logic level of the stored binary information, the voltage level shifter means being connected in parallel to the volatile memory circuit;
a non-volatile storage means for storing said binary information, the information content of the non-volatile storage means being controlled by the elevated logic levels; and
access means for providing access between said non-volatile storage means and said volatile memory circuit, wherein the content of said volatile memory circuit is alterable according to the contents of said non-volatile storage means.
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Abstract
A non-volatile memory circuit for use with an E2 PROM includes redundant, parallel connected, floating node MOSFET memory cells for storing complementary information. The non-volatile memory cells are connected in parallel to a volatile memory circuit via a voltage level shifter circuit for writing operations, and via twin mixed PMOS and NMOS transistors for reading operations. With the combined complementary non-volatile memory cells and the twin mixed pairs of transistors, the stored information is retained in the event that one of the memory cells fails.
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Citations
9 Claims
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1. A non-volatile semiconductor memory system comprising:
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a volatile memory circuit for storing binary information in static form; voltage level shifter means for elevating the logic level of the stored binary information, the voltage level shifter means being connected in parallel to the volatile memory circuit; a non-volatile storage means for storing said binary information, the information content of the non-volatile storage means being controlled by the elevated logic levels; and access means for providing access between said non-volatile storage means and said volatile memory circuit, wherein the content of said volatile memory circuit is alterable according to the contents of said non-volatile storage means. - View Dependent Claims (2, 3, 4)
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5. A non-volatile semiconductor memory system comprising:
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volatile memory circuit for storing binary information in static form; voltage level shifter means for elevating the logic level of the stored binary information, the voltage level shifter means being connected in parallel with the volatile memory circuit; a non-volatile storage means, including two floating node MOSFET memory cells connected in parallel in reverse orientation for storing the binary information in complimentary states, the information content of two floating node MOSFET memory cells being controlled by the elevated logic levels; and access means, including twin mixed parallel coupled pairs of PMOS transistors and NMOS transistors, for providing the access between the non-volatile storage means and the volatile memory circuit so that the contents of the volatile memory circuit is alterable in accordance with the contents of the non-volatile storage means.
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6. A non-volatile semiconductor memory system comprising:
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at least two non-volatile memory cells connected in parallel with opposing orientations, each cell having a node electrode; and two access transistors, one of the NMOS type and one of a PMOS type, the node of each of which is connected to the node electrode of one of the non-volatile memory cells such that each cell is connected to form parallel-connected transistors pairs of mixed transistor types. - View Dependent Claims (9)
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7. A non-volatile semiconductor memory system comprising:
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at least two non-volatile memory cells connected in parallel, each cell having a node electrode and each cell having an orientation similar to the other cell; and two access transistors, one of the NMOS type and one of a PMOS type, the node of each of which is connected to the node electrode of one of the nonvolatile memory cells such that each cell is connected to a mixed pair of transistors to form parallel connected transistor pairs of the same transistor type. - View Dependent Claims (8)
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Specification