Non-volatile memory structure

• US 5,097,449 A
• Filed: 03/15/1990
• Issued: 03/17/1992
• Est. Priority Date: 03/15/1990
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Cuevas, Yongbum P.
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US07/494,007
• Time in Patent Office: 733 Days
• Field of Search: 365/154, 365/185, 365/189.01, 365/230.01, 365/189.05, 365/230.08, 365/228
• US Class Current: 365/185.07
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 14/00 Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
• CPC Class Codes: G11C 14/0063 and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 29/74 using duplex memories, i.e. using dual copies

Abstract

A non-volatile memory circuit for use with an E² PROM includes redundant, parallel connected, floating node MOSFET memory cells for storing complementary information. The non-volatile memory cells are connected in parallel to a volatile memory circuit via a voltage level shifter circuit for writing operations, and via twin mixed PMOS and NMOS transistors for reading operations. With the combined complementary non-volatile memory cells and the twin mixed pairs of transistors, the stored information is retained in the event that one of the memory cells fails.

Claims

1. A non-volatile semiconductor memory system comprising:

a volatile memory circuit for storing binary information in static form;

voltage level shifter means for elevating the logic level of the stored binary information, the voltage level shifter means being connected in parallel to the volatile memory circuit;

a non-volatile storage means for storing said binary information, the information content of the non-volatile storage means being controlled by the elevated logic levels; and

access means for providing access between said non-volatile storage means and said volatile memory circuit, wherein the content of said volatile memory circuit is alterable according to the contents of said non-volatile storage means.

2. A non-volatile semiconductor memory system according to claim 1, wherein:

the non-volatile storage means includes two floating node MOSFET memory cells that are connected in parallel in reverse orientation for storing complimentary information.

3. A non-volatile semiconductor memory system according to claim 2, wherein:

said floating node MOSFET memory cells are single polysilicon layer devices.

4. A non-volatile semiconductor memory system according to claim 3, wherein:

said single polysilicon memory cells include a floating polysilicon node, a tunnel node for supplying a tunnel current to and inducing a potential in said floating node, and a coupling node for inducing a potential on said floating node.

5. A non-volatile semiconductor memory system comprising:

volatile memory circuit for storing binary information in static form;

voltage level shifter means for elevating the logic level of the stored binary information, the voltage level shifter means being connected in parallel with the volatile memory circuit;

a non-volatile storage means, including two floating node MOSFET memory cells connected in parallel in reverse orientation for storing the binary information in complimentary states, the information content of two floating node MOSFET memory cells being controlled by the elevated logic levels; and

access means, including twin mixed parallel coupled pairs of PMOS transistors and NMOS transistors, for providing the access between the non-volatile storage means and the volatile memory circuit so that the contents of the volatile memory circuit is alterable in accordance with the contents of the non-volatile storage means.

6. A non-volatile semiconductor memory system comprising:

at least two non-volatile memory cells connected in parallel with opposing orientations, each cell having a node electrode; and

two access transistors, one of the NMOS type and one of a PMOS type, the node of each of which is connected to the node electrode of one of the non-volatile memory cells such that each cell is connected to form parallel-connected transistors pairs of mixed transistor types.

9. A non-volatile memory system according to claim 6, further comprising:

a voltage level shifter means connected in parallel to the non-volatile memory cells for electrically writing information into said cells.

7. A non-volatile semiconductor memory system comprising:

at least two non-volatile memory cells connected in parallel, each cell having a node electrode and each cell having an orientation similar to the other cell; and

two access transistors, one of the NMOS type and one of a PMOS type, the node of each of which is connected to the node electrode of one of the nonvolatile memory cells such that each cell is connected to a mixed pair of transistors to form parallel connected transistor pairs of the same transistor type.

8. A non-volatile memory system according to claim 7 further comprising:

voltage level shifter means connected in parallel to the non-volatile memory cells for electrically writing information into said cells.