Circuit for enabling a cache using a flush input to circumvent a late noncachable address input
First Claim
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1. A computer system, comprising:
- a processor having address and data lines;
cache memory coupled to said address and data lines;
a cache controller coupled to said processor and to said cache memory including a means for developing an internal clock signal and having a noncachable address input which is sampled too late, allowing operations that access memory address space designated as noncachable to be performed by said cache memory, and a flush input which clears the validity status of said cache memory;
a register coupled to said processor for storing a desired enabled state of said cache controller and providing a signal indicative thereof; and
means for synchronizing said desired enabled state signal to said internal clock signal of said cache controller, said synchronized desired enabled signal being connected to said cache controller flush input to clear the validity status of said cache memory so that operations that access memory address space designated as noncachable are not performed by said cache memory.
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Abstract
A circuit for generating a synchronized flush signal for use with a cache controller which samples the noncachable address input too late for that input to be used to disable the cache controller is described. The circuit synchronizes a memory-mapped register bit with the internal clock signal in the cache controller to insure setup and hold times and proper phasing. The use of the synchronized flush signal overcomes coherency problems with the noncachable input.
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7 Claims
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1. A computer system, comprising:
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a processor having address and data lines; cache memory coupled to said address and data lines; a cache controller coupled to said processor and to said cache memory including a means for developing an internal clock signal and having a noncachable address input which is sampled too late, allowing operations that access memory address space designated as noncachable to be performed by said cache memory, and a flush input which clears the validity status of said cache memory; a register coupled to said processor for storing a desired enabled state of said cache controller and providing a signal indicative thereof; and means for synchronizing said desired enabled state signal to said internal clock signal of said cache controller, said synchronized desired enabled signal being connected to said cache controller flush input to clear the validity status of said cache memory so that operations that access memory address space designated as noncachable are not performed by said cache memory. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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Specification