Multi-channel analogue to digital convertor

• US 5,099,239 A
• Filed: 09/21/1989
• Issued: 03/24/1992
• Est. Priority Date: 09/21/1989
• Status: Expired due to Term

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: Bruce, Richard H., Senderowicz, Daniel, Lewis, Alan G.
• Primary Examiner(s): Fuller, Benjamin R.
• Assistant Examiner(s): Gibson, Randy W.
• Application Number:
  US07/410,566
• Time in Patent Office: 915 Days
• Field of Search: 341/155, 341/128, 341/166, 341/167, 341/161, 357/24
• US Class Current: 341/155
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 1/468 in which the input S/H circuit is merged with the feedback DAC array
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

A multichannel ADC is fabricated on a single IC with each analog channel for concurrently processing input analogue signal in a pipelined manner and including a dual purpose intermediate amplifier for amplifying an input voltage to be converted and providing a reference voltage for use during conversion. A unique capacitor array reduces the area required to implement the convertors.

Claims

1. A multichannel analog to digital convertor (ADC) formed on a single IC chip comprising:

a plurality of parallel ADC channels disposed on the single IC chip, each parallel channel including an analog signal path and capacitor array circuitry for converting an accepted analog signal of an unknown amplitude to a digital representation encoding a value of the amplitude of the accepted signal and each channel for accepting one analog input signal from a plurality of analog input signals at a selected time, each channel for concurrently converting each accepted analog input signal to a digital representation; and

digital signal paths, separated from said analog signal paths and coupled to the capacitor array circuitry of each ADC channel, for transmitting digital control signals to the capacitor array circuitry.

3. The ADC of claim 1 or 2 wherein the single IC chip includes an output port and further comprising:

digital means for transferring said converted digital representations to the output port.

4. The ADC of claims 1 or 2 wherein the circuitry for accepting an analog signal in each ADC channel further comprises:

an input amplifier having an input port; and

an input switch for coupling said input port directly to an external source when the external source is providing an analog input charge signals and for coupling said input port to an input capacitor when the external source is providing an input analog voltage signal, where said input capacitor is previously charged to said input analog voltage.

5. The ADC of claims 1 or 2 wherein each ADC channel further comprises:

an input stage for accepting an analog input charge from an external source characterized by a large external capacitance and for generating an input voltage signal;

a second processing stage following said input stage; and

an input switch for decoupling said large external capacitance prior to transferring said input voltage signal from said input stage to said second stage.

6. The ADC of claims 1 or 2 further including an on-chip bias voltage generation and distribution system comprising:

a first reference voltage generator, having an initial voltage input coupled to receive a fixed voltage and having an output port, for generating a first reference voltage differing from said fixed voltage by a first offset value;

a second reference voltage generator, having an initial voltage input coupled to the output port of said first reference voltage level generator to receive said first reference voltage and having an output port, for generating a second reference voltage differing from said first reference voltage by a second offset value so that the difference between said first and second reference voltages is not affected by errors generated by said first reference voltage generator.

7. The ADC of claim 3 wherein:

said digital means is a digital shift register including a plurality of stages for accepting said converted digital representations and subsequently shifting said accepted digital representations to the output port.

2. A multichannel analog to digital convertor (ADC) formed on a single IC chip comprising:

a plurality of at least 10 parallel ADC channels disposed on the single IC chip, each parallel channel including an analog signal path and capacitor array circuitry for converting an accepted analog signal of an unknown amplitude to a digital representation encoding a value of the amplitude of the accepted signal and each channel for accepting one analog input signal from a plurality of analog input signals at a selected time, each channel for concurrently converting each accepted analog input signal to a digital representation; and

digital signal paths, separated from said analog signal paths and coupled to the capacitor array circuitry of each ADC channel, for transmitting digital control signals to the capacitor array circuitry.

8. The multichannel analog to digital convertor (ADC) formed on a single IC chip comprising:

a plurality of ADC channels disposed on the single IC chip, each channel for accepting one analog input signal from a plurality of analog input signals and for concurrently converting each accepted analog input signal to a digital representation;

digital data transfer means for transferring said converted digital representations to the output port;

digital control means for generating digital control signals to control the operation of said channels and said digital transfer means;

digital signal transfer means for transferring digital control signals to said channels and said digital data transfer means where said digital data transfer means and said channels are disposed on separate isolated areas of the chip and said digital signal transfer means are isolated from said channels except at connection points of digital control signals required by a channel.

9. A multichannel analog to digital convertor (ADC) formed on a semiconductor integrated circuit comprising:

a plurality of parallel ADC channels, each channel including an input integrator stage, that accepts an analog input charge from an external source, for generating an input voltage signal indicating a magnitude of the analog input charge, a dual function amplifier stage, under control of a first digital signal, for amplifying the input voltage signal when the first digital signal is set and said amplifier stage is coupled to said integrator to generate an amplified input voltage signal and for providing a buffered first reference voltage when the first digital signal is reset and said amplifier stage is decoupled from said integrator, and a convertor stage, under control of a second digital signal, for storing said amplified input voltage state when said second digital signal is set and for utilizing said buffered first reference voltage to convert said stored amplified input voltage to a digital representation when said second digital signal is reset;

digital control means for setting and resetting said first and second digital signals, decoupling said amplifier stage from said integrator, and coupling said integrator to the external source during a first time period so that, during said first time period, said convertor stage utilizes said buffered reference voltage signal to convert a first amplified input voltage to a digital representation while said integrator stage generates a second input voltage signal and for coupling said amplifier to said integrator, decoupling said integrator from the external source, and controlling the states of said first and second digital signals during a second time period so that said amplifier stage amplifies said second input voltage signal and said convertor stage stores said amplified second input voltage signal during said second time period; and

a digital shift register for accepting the digital representations of said first amplified input signal during said second time period from said plurality of ADC channels and for shifting said accepted digital representations to an ADC output port during a third time period when said second input voltage signal is being converted.

10. A multichannel analog to digital convertor (ADC) formed on a semiconductor integrated circuit comprising:

a plurality of parallel ADC channels, each channel including an input integrator stage, that accepts an analog input signal from an external source, for generating an input voltage signal indicating a magnitude of the analog input signal, a dual function intermediate amplifier stage, under control of a first digital signal, for amplifying the input voltage signal when the first digital signal is set and said intermediate amplifier stage is coupled to said input amplifier stage to generate an amplified input voltage signal and for providing a buffered first reference voltage when the first digital signal is reset and said intermediate amplifier stage is decoupled from said input amplifier, and a convertor stage, under control of a second digital signal, for storing said amplified input voltage state when said second digital signal is set and for utilizing said buffered first reference voltage to convert said stored amplified input voltage to a digital representation when said second digital signal is reset;

digital control means for setting and resetting said first and second digital signals, decoupling said intermediate amplifier stage from said input amplifier, and coupling said input amplifier to the external source during a first time period so that, during said first time period, said convertor stage utilizes said buffered reference voltage signal to convert a first amplified input voltage to a digital representation while said input amplifier stage generates a second input voltage signal and for coupling said intermediate amplifier to said integrator, decoupling said input amplifier from the external source, and controlling the states of said first and second digital signals during a second time period so that said intermediate amplifier stage amplifies said second input voltage signal and said convertor stage stores said amplified second input voltage signal during said second time period; and

a digital shift register for accepting digital representations of said first amplified input signal during said second time period from said plurality of ADC channels and for shifting said accepted digital representations to an ADC output port during a third time period when said second input voltage signal is being converted.

11. The ADC of claim 10 wherein said input amplifier stage includes an input port and further comprises:

an input capacitor;

an input switch for coupling said input port directly to an external source when the external source is providing an analog input charge signal and to said input capacitor when the external source is providing an input analog voltage signal, where said input capacitor is subsequently charged to said input analog voltage.

12. A channel for converting a received analogue charge signal from an external source into a digital signal representing the magnitude of the received analogue charge signal, said channel comprising:

an integrator, having a first switch, an input that receives the analogue charge signal when coupled to the external source, and an output port for providing an analogue input voltage signal indicating the magnitude of the analogue charge signal to said input port when said first switch is open and for providing a first reference voltage when said first switch is closed;

an intermediate amplifier, including an input capacitor having a first plate coupled to the output port of said integrator by a second switch, a third switch, and an output port, for providing an amplified signal at the amplifier output port when said third switch is open and for providing said reference voltage when said third switch is closed;

a conversion stage coupled to the output port of said intermediate amplifier for storing the amplified signal provided by said amplifier and for utilizing the reference voltage provided by said intermediate amplifier to convert said stored amplified signal to a digital representation;

means for coupling said integrator to the source and opening said first switch during a first time interval to integrate a second analogue charge signal and generate a second analogue input voltage signal, for closing said third switch to provide said reference voltage, and for controlling said conversion stage to utilize said provided reference voltage to convert a first amplified signal to a digital representation during said first time interval;

means for decoupling said integrator from said source and closing said second switch during a second time interval to charge said input capacitor to said second analogue input voltage signal level;

means for closing said first switch to provide said reference voltage to the first plate of said input capacitor and opening said third switch to amplify said second input voltage signal to a second amplified signal during a third time interval, for controlling said conversion stage to store said second amplified signal during said third time interval, and for coupling said integrator to the source and opening said first switch so that a third analogue charge signal is integrated during said first time interval.

13. A multichannel ADC formed on a semiconductor integrated circuit comprising:

a plurality of parallel ADC channels each including an input stage for accepting a series of first, second and third analog input signals and generating associated first, second and third input voltage signals indicating magnitude of the analogue input signals and a convertor stage for converting said input voltage signals to a digital representation;

means for controlling said input stage to accept said third analog input signal and generating said third associated input voltage signal during a given time interval while said convertor stage is converting the second input voltage signal associated with said second analog input signal.

14. The ADC of claim 13 including an output port and further comprising:

digital transfer means for transferring a digital representation of a first analogue input signal to the output port during said given time interval.