Method and apparatus for limiting the utilization of an asynchronous bus with distributed controlled access

• US 5,099,420 A
• Filed: 01/10/1989
• Issued: 03/24/1992
• Est. Priority Date: 01/10/1989
• Status: Expired due to Term

• Current Assignee: Honeywell Bull Incorporated (Atos SE)
• Original Assignee: Bull HN Information Systems Incorporated (Atos SE)
• Inventors: Bradley, John W., Barlow, George J., Getson, Edward F. Jr.
• Primary Examiner(s): Cangialosi, Salvatore
• Application Number:
  US07/295,639
• Time in Patent Office: 1,169 Days
• Field of Search: 364/240.5, 370/85, 340/825.5
• US Class Current: 710/119
• CPC Class Codes: G06F 13/368 with decentralised access control

Abstract

A plurality of units which are coupled to transfer requests, transfer data over an asynchronous bus network during allocated bus transfer cycles. The network has a tie-breaking bus priority network which is distributed to a common interface portion of each of the plurality of units and grants bus cycles and resolves simultaneous requests on a priority basis. At least one unit includes bus saturation detection apparatus included within its common interface portion for monitoring bus activity over established intervals of time. The detection of the occurrence of at least one available cycle over the given interval of time signals that the bus network is not in a saturated state. When the indicator specifies that the bus network is saturated, the unit throttles down its operation by increasing the amount of time between issuing data requests. Throttling continues until the bus is no longer being saturated.

Claims

1. Bus saturation apparatus for detecting saturation on an asynchronous bus network coupled in common to a plurality of data handling units during the asynchronous transfer of data between different ones of said units during bus cycles of operation granted on a priority basis controlled by a priority network included as part of said bus network, said priority network being distributed to each of said plurality of units, said bus saturation apparatus being included in at least one of said units, said apparatus comprising:

means coupled to said bus network for monitoring the state of a predetermined one of a number of lines of said bus network indicative of bus activity; and

,

bistate indicator means coupled to said monitoring means, said indicator means being set to a predetermined state at a start of a data transfer interval by said one unit and said bistate indicator means being switched to another state by said monitoring means when said monitoring means detects that said bus network is not being saturated.

2. The apparatus of claim 1 wherein said monitoring means includes means for detecting an occurrence of an unused bus cycle of operation.

3. The apparatus of claim 2 wherein said monitoring means includes delay circuit means coupled to said predetermined one of said number of lines, said delay circuit means delaying signals received from said predetermined one of said lines by an amount corresponding to a normal interval between successively granted bus cycles for maintaining said indicator means in said predetermined state enabling detection of said unused bus cycle of operation.

4. The apparatus of claim 1 wherein said indicator means has an input and an output, said one unit including processor means coupled to said input and said output, said processor means applying a signal to said input at said start of said data transfer interval for switching said indicator means to said predetermined state and said processor means generating signals at a completion of said data transfer interval to test the state of said indicator means.

5. The apparatus of claim 4 wherein said predetermined one of said lines receives signals corresponding to bus data cycle now signals indicating when data cycles are taking place on said bus network.

6. The apparatus of claim 3 wherein said processor means generates signals for repeatedly setting said indicator means to said predetermined state prior to said start of each successive data transfer interval and testing said indicator means at said completion of said each data transfer interval for determining if said processor means had caused bus saturation during a previous data transfer interval.

7. The apparatus of claim 6 wherein said processor means includes microprogrammed control means for storing sequences of microinstructions for controlling the transfer of data between said unit and said bus network, said sequences including test and branch microinstructions, each including a branch address and first and second fields coded to specify said testing of said state of indicator means, and said processor means upon determining that said indicator means is in said predetermined state branching to a sequence of microinstructions specified by said branch address for throttling down said transfer of data between said unit and said bus network.

8. The apparatus of claim 7 wherein said unit further includes bus request means coupled to said processing means for generating requests for accessing said bus network for transferring data between said unit and said bus network, said processor means in response to said sequence of microinstructions delaying said generating of each request by a predetermined amount so as to reduce an amount of data being transferred between said unit and said bus network for said throttling down said transfer of data.

9. The apparatus of claim 8 wherein each said request is coded to specify a burst type of operation in which said processor means transfers a successive number of byte groups of data over said bus network during a corresponding number of allocated bus cycles of operation.

10. The apparatus of claim 8 wherein said predetermined amount of delay is defined by a wait count value stored by said processor means, said processor means incrementing said wait count by one each time said indicator means is detected to be in said predetermined state following said data transfer interval and said processor means continuing said throttling down said transfer of data by causing said bus request means to increase said delaying said generating of each said request until said indicator means is detected to have switched from said predetermined state to said another state.

11. The apparatus of claim 10 wherein said bus request means includes means for specifying the priority of said requests being generated, said processor means upon incrementing said wait count value to a predetermined value switching said means for specifying said priority from a high to a low priority further throttling down said transfer of data.

12. The apparatus of claim 10 wherein said processor means upon detecting that said indicator means has switched to said another state resets said wait count value to zeros enabling said transfer of data to be resumed at a maximum rate.

13. A peripheral controller for controlling the high speed transfer of data from at least one input/output device to and from an asynchronous bus network which connects said controller common with a plurality of data handling units for asynchronously transferring data between different ones of said units during bus cycles of operation granted on a priority basis controlled by a priority network included as part of said bus network, said priority network being distributed to each of said plurality of units, said controller comprising:

a bus saturation detector coupled to said bus network, said detector including;

means coupled to said bus network for monitoring the state of a predetermined one of a number of lines of said bus network indicative of bus activity; and

,

a bistable indicator coupled to said monitoring means, said bistable indicator being switched from a first state to a second state by said monitoring means when said monitoring means detects that said bus network is not being saturated; and

,

processor means for generating signals for transferring blocks of data between said input/output device and said bus network, said processor means being coupled to said bus saturation detector, said processor means setting said indicator to said first state at a start of a data transfer operation interval and said processor means including means for testing said state of said indicator at a completion of said data transfer operation interval.

14. The controller of claim 13 wherein said monitoring means includes means for detecting an occurrence of an unused bus cycle of operation.

15. The controller of claim 14 wherein said monitoring means includes delay circuit means coupled to said predetermined one of said number of lines, said delay circuit means delaying signals received from said predetermined one of said lines by an amount corresponding to a normal interval between successively granted bus cycles for maintaining said indicator in said first state enabling detection of said unused bus cycle of operation.

16. The controller of claim 15 wherein said predetermined one of said lines receives signals corresponding to bus data cycle now signals indicating when data cycles are taking place on said bus network.

17. The controller of claim 13 wherein said processor means generates signals for repeatedly setting said indicator to said first state prior to said start of each successive data transfer operation interval and testing said indicator means at said completion of said each data transfer operation interval for determining if said processor means had caused said bus network to saturate during a previous data transfer operation interval.

18. The controller of claim 17 wherein said processor means includes microprogrammed control means for storing sequences of microinstructions for controlling the transfer of data between said input/output device and said bus network, said sequences including test and branch microinstructions, each including a branch address and first and second fields coded to specify said testing of said state of indicator, and said processor means upon determining that said indicator means is in said first state branching to a sequence of microinstructions specified by said branch address for throttling down said transfer of data between said device and said bus network.

19. The controller of claim 18 wherein said controller further includes bus request means coupled to said processing means for generating requests for accessing said bus network for transferring data between said device and said bus network, said processor means in response to said sequence of microinstructions delaying said generating of each request by a predetermined amount so as to reduce an amount of data being transferred between said device and said bus network for said throttling down said transfer of data.

20. The controller of claim 19 wherein each said request is coded to specify a burst type of operation in which said processor means transfers a successive number of byte groups of data over said bus network during a corresponding number of allocated bus cycles of operation.

21. The controller of claim 19 wherein said predetermined amount of delay is defined by a wait count value stored by said processor means, said processor means incrementing said wait count by one each time said indicator is detected by testing to be in said first state following said data transfer operation interval and said processor means continuing said throttling down said transfer of data by causing said bus request means to increase said delaying said generating of each said request until said indicator means is detected to have switched from said first state to said second state or until said wait count has reached a predetermined maximum value.

22. The controller of claim 21 wherein said bus request means includes means for specifying the priority of said requests being generated, said processor means upon incrementing said wait count value to a predetermined value switching said means for specifying said priority from a high to a low priority further throttling down said transfer of data.

23. The controller of claim 21 wherein said processor means upon detecting that said indicator has switched to said second state resets said wait count value to zeros enabling said controller to resume said transfer of data at a maximum rate.

24. A method of preventing the saturation of an asynchronous bus network coupled in common to a plurality of data handling units in which data is asynchronously transferred between different ones of said units during bus cycles of operation granted on a priority basis controlled by a priority network includes as part of said bus network, said priority network being distributed to each of said plurality of units, said method comprising the steps of:

including as part of a bus interface of each of a number of said units, a bus saturation detector circuit;

monitoring bus cycle activity by connecting an input of said bus saturation detector to a predetermined line of said bus network;

setting said detector circuit to a first state at the start of a data transfer by a processor included in said each of a number of units;

switching said detector circuit from said first state to a second state when said detector circuit detects an occurrence of an unused bus cycle;

testing the state of said detector circuit at the end of said data transfer interval by said processor for determining if said bus network is being saturated; and

,

throttling down the rate at which data is being transferred by said processor in a predetermined manner when the state of said detector circuit indicates that said bus network is saturated until said bus network is no longer being saturated.