Switching system

• US 5,099,475 A
• Filed: 08/09/1990
• Issued: 03/24/1992
• Est. Priority Date: 09/14/1989
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Endo, Noboru, Sakurai, Yoshito, Kozaki, Takahiko
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): KIZOU, HASSAN
• Application Number:
  US07/564,617
• Time in Patent Office: 593 Days
• Field of Search: 370/60, 370/94.1, 370/61, 370/58.1, 370/91, 370/92, 370/112, 370/84, 370/60.1
• US Class Current: 370/422
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/5672 Multiplexing, e.g. coding, scrambling
• CPC Class Codes: H04L 49/108 using shared central buffer
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

A switching system for switching communication information between "M" incoming highways and "N" outgoing highways by using fixed-length cells, each having a header section and a data section and according to information contained in the header section (where "M" and "N" are integers), comprising: a demultiplexing unit for demultiplexing each incoming highway into a plurality of first output links; a switch unit, having the first output links of the demultiplexing unit as first input links and a plurality of second output links, for switching communication information between the first input links and the second output links; and a multiplexing unit, having "N" groups of input links, each group being formed by grouping a specified number of second output links, for multiplexing the cells on the second output links of each group and outputting them through one of third output links to a corresponding outgoing highway.

Claims

1. A switching system for switching communication information between "M", where "M" is an integer, incoming highways and "N", where "N" is an integer, outgoing highways by using fixed-length cells, each cell having a header section and a data section, switching of each cell being performed according to information contained in said head section, comprising:

a demultiplexing unit for demultiplexing each incoming highway into a plurality of first output links;

a switch unit, having the first output links of said demultiplexing unit as first input links and a plurality of second output links, for switching communication information between said first input links and said second output links; and

a multiplexing unit, having "N" groups of second input links, each group being formed by grouping a specified number of second output links of said switch unit as said "N" groups of second input links, and "N" third output links, for multiplexing the cells on the second input links of each group and outputting each cell through one of said third output links to one corresponding outgoing highway;

wherein said demultiplexing means includes means for outputting the cells input from the incoming highways by sequentially distributing said cells to said plurality of first output links in the order of arrival, wherein said first memory means includes means for outputting, in the order of input, the cells to said specified number of second input links of each of "N" groups of second input links of said multiplexing means, and wherein said multiplexing means includes means for outputting, in the order of input, the cells input into said specified number of second input links to corresponding third output links.

2. A switching system for processing a plurality of cells, each cell including a header section and a data section, and for switching communication information contained in the data section of the cell between "M", where "M" is an integer, incoming highways and "N", where "N" is an integer, outgoing highways according to the data contained in the header section of the cell, comprising:

demultiplexing means for demultiplexing each incoming highway into a plurality of first output links;

first memory means, having the first output links of said demultiplexing means as first input links, a plurality of second output links and addressable storage locations for storing the cells received through said first output links from said demultiplexing means, for switching information between said first output links and second output links according to information contained in said header section;

multiplexing means, having "N" groups of second input links, each group being formed by grouping a specified number of said second output links of said first memory means, and "N" third output links, for outputting the cells on said second input links through one of said third output links to one corresponding outgoing highway; and

means for controlling write operations of said first memory means in accordance with an address identifying an empty storage location of said first memory means;

wherein said demultiplexing means includes means for outputting the cells input from the incoming highways by sequentially distributing said cells to said plurality of first output links in the order of arrival, wherein said first memory means includes means for outputting, in the order of input, the cells to said specified number of second input links of each of "N" groups of second input links of said multiplexing means, and wherein said multiplexing means includes means for outputting, in the order of input, the cells input into said specified number of second input links to corresponding third output links.

3. A switching system for processing a plurality of cells, each cell including a header section and a data section, and for switching communication information contained in the data section of the cell between "M", where "M" is an integer, incoming highways and "N", where "N" is an integer, outgoing highways according to the data contained in the header section of the cell, comprising:

demultiplexing means for demultiplexing each incoming highway into a plurality of first output links;

first memory means, having the first output links of said demultiplexing means as first input links, a plurality of second output links and addressable storage locations for storing the cells received through said first output links from said demultiplexing means, for switching information between said first output links and second output links according to information contained in said header section;

multiplexing means, having "N" groups of second input links, each group being formed by grouping a specified number of said second output links of said first memory means, and "N" third output links, for outputting the cells on said second input links through one of said third output links to one corresponding outgoing highway; and

second memory means for storing an address identifying an empty storage location of said first memory means; and

means for controlling write operations of said first memory means in accordance with said address stored in said second memory means;

wherein said demultiplexing means includes means for outputting the cells input from the incoming highways by sequentially distributing said cells to said plurality of first output links in the order of arrival, wherein said first memory means includes means for outputting, in the order of input, the cells to said specified number of second input links of each of "N" groups of second input links of said multiplexing means, and wherein said multiplexing means includes means for outputting, in the order of input, the cells input into said specified number of second input links to corresponding third output links.

4. A switching system according to claim 3, wherein said controlling means includes first means for storing in said first memory means said address from said second memory means as a next address at which data is to be stored along with a cell received from said demultiplexing means, and means for storing said address for use as a write address to store the next cell received from said demultiplexing means for a given outgoing highway in said first memory means.

5. A switching system according to claim 4, wherein said controlling means further includes second means for storing said next address read out of said first memory means at the time a cell is read out of said first memory means for a given outgoing highway, and means for reading another cell from said first memory means for said given outgoing highway using said next address stored in said second means.

6. A switching system according to claim 5, wherein said controlling means also includes means for storing said next address in said second means into said second memory means when that address is used to read said another cell from said first memory means.

7. A switching system for switching communication information between "M" where "M" is an integer, incoming highways for transmitting cells at a bit rate of m×

v, where "m" is an integer and "v" is a positive integer and "N", where "N" is an integer, outgoing highways for transmitting the cells at a bit rate of n×

v'"'"', where "n" is an integer and "v'"'"'" is a positive integer, by using fixed-length cells, each cell having a header section and a data section, said cells are input from each incoming highway and each cell is switched according to information contained in said header section, comprising;

"M" demultiplexing units, provided to correspond with said "M" incoming highways, each demultiplexing unit has "m" first output links, each demultiplexing unit, on receiving "m" cells at a bit rate of m×

v from a corresponding incoming highway, demultiplexing the cells into the "m" first output links and outputs the cells one after another at a bit rate of b to each first output link;

a switching unit, having "M" groups of "m" first output links of said "M" demultiplexing units as "M" groups of "m" first input links with a bit rate of v and "N" groups of "n" second output links with a bit rate of v, for switching communication information between said first input links and said second output links according to information contained in said header section of each cell; and

"N" multiplexing units, provided to correspond with "N" outgoing highways, each multiplexing unit has a third output link, each multiplexing unit being capable of receiving cells from "n" corresponding second output links of said switch unit, multiplexing "n" cells supplied at a bit rate of v on said "n" second output links, and outputting the cells at a bit rate of n×

v to third output links to output the cells to the corresponding outgoing highways;

each demultiplexing unit includes means for outputting the cells from the incoming highway thereof by sequentially distributing said cells to said "m" first output links in the order of arrival, wherein said switch unit includes means for outputting the cells to said "n" second output links in the order of the cells being input into said switch unit; and

each multiplexing unit includes means for outputting the cells received from said "n" second output links to one corresponding third output link in the order of input.

8. A switching system according to claim 7, wherein said switching unit includes means for multiplexing cells on said "M" groups of "m" first input links in time division, first memory means having addressable storage locations for storing cells received from said demultiplexing units means for demultiplexing and distributing data output from said first memory means among said "N" groups of "n" second output links, second memory means for storing an address identifying an empty storage location of the first memory means, and means for controlling the write operations of said first memory means in accordance with said address stored in the second memory means.

9. A switching system according to claim 8, wherein said controlling means includes first means for storing in said first memory means said address from said second memory means as next address at which data is to be stored along with a cell received from said multiplexing means, and means for storing said address for use as a write address to store the next cell received from said multiplexing means for a given outgoing highway in said first memory means.

10. A switching system according to claim 9, wherein said controlling means further includes second means for storing said next address read out of said first memory means at the time a cell is read out of said first memory means for a given outgoing highway, and means for reading another cell from said first memory means for said given outgoing highway using said next address stored in said second means.

11. A switching system according to claim 10, wherein said controlling means also includes means for storing said next address in said second means into said second memory means when that address is used to read said another cell from said first memory means.

12. A switching system according to claim 8, wherein said multiplexing means and said second memory means of said switching unit, and said demultiplexing means are formed on an LSI board.

13. A switching system according to claim 10, wherein said second means of said controlling means of said switching unit, and said multiplexing means, said second memory means, and said demultiplexing means of said switching unit are formed on an LSI board.

14. A switching system according to claim 12, wherein said LSI board is divided into components which correspond to the number of bits of a cell input in parallel to the switching unit.

15. A switching system according to claim 7, wherein each cell input from said incoming highway has a logical channel number in the header section, and wherein each demultiplexing unit includes outgoing highway number adding means for deciding an outgoing highway number for a given cell according to the logical channel number of the cell input and adding that outgoing highway number to the cell as a header for the switching unit used in the switching system, and logical channel number converting means for converting said logical channel number to a new logical channel number which the cell uses at the outgoing highway.