Registered RAM array with parallel and serial interface

• US 5,099,481 A
• Filed: 02/28/1989
• Issued: 03/24/1992
• Est. Priority Date: 02/28/1989
• Status: Expired due to Term

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Miller, Michael J.
• Primary Examiner(s): Chan, Eddie P.
• Assistant Examiner(s): FAGAN, MATTHEW
• Application Number:
  US07/317,001
• Time in Patent Office: 1,120 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 371/22.1, 371/21.1
• US Class Current: 714/724
• CPC Class Codes: G06F 11/25 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 11/348 Circuit details, i.e. tracer hardware
• CPC Class Codes: G11C 29/20 using counters or linear-feedback shift registers [LFSR]
• CPC Class Codes: G11C 29/30 Accessing single arrays

Abstract

A serial protocol register and an initialization counter are configured to initialize (program) a RAM array. The register is configured to receive, in serial format, an initial address to be loaded into the counter. Also, the register is configured to receive, in serial format, a series of machine states (data words), each to be stored in the RAM array. In addition, the register is configured to clock the counter following each received machine state. The counter is configured to develop a series of addresses, each for accessing the RAM array to store in the array a corresponding one of the machine states.

Claims

1. A registered RAM system for receiving an externally generated serial bit stream signal that includes both a command portion representing in serial format a command and a data words portion representing in serial format both an initial address and a plurality of machine states, for receiving an externally generated plurality of signals representing a first series of RAM array addresses, for receiving an externally generated serial bit stream clocking signal, and for receiving an externally generated command/data signal, said registered RAM system comprising in combination:

a serial protocol register for receiving the serial bit stream signal, for converting from serial to parallel format the command, the initial address, and at least some of said machine states, for developing a plurality of signals representing the parallel format initial address and parallel format machine states, for developing a first counter clocking signal, and for developing a counter loading signal, said serial protocol register including,

first coupling means,

a command register having a clock input coupled by said first coupling means to receive the serial bit stream clocking signal, a serial data input coupled to receive the command portion of said serial bit stream signal, and a predetermined number of parallel data outputs at which said command register develops a plurality of signals representing said parallel format command,

a command decoder having a predetermined number of parallel data inputs coupled to said command register to receive at least a predetermined number of said parallel format command signals, said command decoder for developing said counter loading signal,

second coupling means,

a data register having a clock input coupled by said second coupling means to receive said serial bit stream clocking signal, a serial data input coupled to receive the data words portion of said serial bit stream signal, and a predetermined number of parallel data outputs at which said data register develops a plurality of signals representing said parallel format initial address and said parallel format machine states,

an initialization counter connected to said serial protocol register to receive said counter loading signal and to receive said parallel format initial address signals at a time delineated by said counter loading signal and coupled to said serial protocol register to receive said first counter clocking signal, said initialization counter being clocked by said first counter clocking signal to develop a plurality of signals representing a second series of RAM array addresses;

a first multiplexer including a first set of data inputs to receive the first series of RAM array addresses signals, a second set of data inputs connected to said initialization counter to receive said second series of RAM array addresses signals, and a set of data outputs at which said first multiplexer develops a plurality of signals representing a selected one of said first and said second series of RAM array addresses signals;

a RAM array including a plurality of storage locations, said RAM array coupled to said first multiplexer to receive said selected one of first and second series of RAM array addresses signals and coupled to said serial protocol register to receive said parallel format machine states signals, said RAM array for storing said parallel format machine states each at a respective one of said storage locations addressed by a respective one of said second series of RAM array addresses to initialize said RAM array, for retrieving at least some of the stored machine states each stored at one of said storage locations addressed by a respective one of said first series of RAM array addresses, and for developing a plurality of signals representing the retrieved machine states; and

a pipeline register coupled to said RAM array to receive said retrieved machine states signals, for latching the state of each of said retrieved machine states, and for developing a plurality of signals representing the latched machine states.

2. The registered RAM system as recited in claim 1 for further receiving an externally generated second counter clocking signal and externally generated signals representing trace words, wherein said registered RAM system further comprises a second multiplexer including a first data input connected to said serial protocol register to receive said first counter clocking signal, a second data input to receive said second counter clocking signal, and a data output connected to said initialization counter, said second multiplexer developing at said data output a signal representing a selected one of said first and said second counter clocking sigals, and wherein said initialization counter is further clocked by said second counter clocking signal, and wherein said RAM array further stores at least some of said trace words each at a one of said storage locations addressed by a respective one of said second series of RAM array addresses.

3. The registered RAM system as recited in claim 1 wherein said serial bit stream signal data words portion further include at least one breakpoint address, wherein said serial protocol register further converts from serial to parallel format said received breakpoint address, wherein said data register develops said plurality of signals so as to further represent said parallel format breakpoint address, and wherein said registered RAM system further comprises a breakpoint comparator connected to said serial protocol register to receive said parallel format breakpoint address signals and connected to said first multiplexer to receive said first series of RAM array addresses, said breakpoint comparator for developing a signal which indicates when one of said first series of RAM array addresses is the same as said breakpoint address.

4. The registered RAM system as recited in claim 1 wherein said serial bit stream signal data words portion further include at least one breakpoint machine state, wherein said serial protocol register further converts from serial to parallel format said received breakpoint machine state wherein said data register develops said plurality of signals so as to further represent said parallel format breakpont machine state, and wherein said registered RAM system further comprises a breakpoint comparator connected to said serial protocol register to receive said parallel format breakpoint machine state signals and connected to said RAM array to receive said retrieved machine states signals, said breakpoint comparator for developing a signal which indicates when one of said retrieved machine states is the same as said breakpoint machine state.

5. A registered RAM system for receiving an externally generated serial bit stream signal that includes both a command portion representing in serial format a command and a data words portion representing in serial format both an initial address and a plurality of machine states, for receiving an externally generated plurality of signals representing a first series of RAM array addresses, for receiving an externally generated serial bit stream clocking signal, and for receiving an externally generated command/data signal, said registered RAM system comprising in combination:

a serial protocol register for receiving the serial bit stream signal, for converting from serial to parallel format the command, the initial address, and at least some of said machine states, for developing a plurality of signals representing the parallel format initial address and parallel format machine states, for developing a first counter clocking signal, and for developing a counter loading signal, said serial protocol register including,

first coupling means,

a command register having a clock input coupled by said first coupled means to receive the serial bit stream clocking signal, a serial data input coupled to receive the command portion of said serial bit stream signal, a serial data output at which said command register develops a signal representing said command portion of said serial bit stream signal delayed a predetermined number of cycles of said serial bit stream signal clocking signal, and a predetermined number of parallel data outputs at which said command register develops a plurality of signals representing said parallel format command,

a command decoder having a predetermined number of parallel data inputs coupled to said command register to receive at least a predetermined number of said parallel format command signals, said command decoder for developing said counter loading signal,

second coupling means,

a data register having a clock input coupled by said second coupling means to receive said serial bit stream clocking signal, a serial data input coupled to receive the data words portion of said serial bit stream signal, a serial data output at which said data register develops a signal representing at least a portion of said data word portion of said serial bit stream signal delayed a predetermined number of cycles of said serial bit stream signal clocking signal, and a predetermined number of parallel data outputs at which said data register develops a plurality of signals representing said parallel format initial address and said parallel format machine states,

third coupling means, and

a first multiplexer having a first data input coupled by said third coupling means to said command register serial data output to receive said delayed command portion signal, a second input coupled to said data register serial data output to receive said dealyed data word portion signal, a control input coupled to receive the command/data signal, and a data output at which said first multiplexer develops a delayed serial bit stream signal representing a combination of at least said delayed command portion and said delayed data word portion;

an initialization counter connected to said serial protocol register to receive said counter loading signal and to receive said parallel format initial address signals at a time delineated by said counter loading signal and coupled to said serial protocol register to receive said first counter clocking signal, said intialization counter being clocked by said first counter clocking signal to develop a plurality of signals representing a second series of RAM array addresses;

a second multiplexer including a first set of data inputs to receive the first series of RAM array addresses signals, a second set of data inputs connected to said initialization counter to receive said second series of RAM array addresses signals, and a set of data outputs at which said second multiplexer develops a plurality of signals repersenting a selected one of said first and said second series of RAM array addresses signals;

a RAM array including a plurality of storage locations, said RAM array coupled to said second multiplexer to receive said selected one of said first and second series of RAM array addresses signals and coupled to said serial protocol register to receive said parallel format machine states signals, said RAM array for storing said parallel format machine states each at a respective one of said storage locations addressed by a respective one of said second series of RAM array addresses to initialize said RAM array, for retrieving at least some of the stored machine states each stored at one of said storage locations addressed by a respective one of said first series of RAM array addresses, and for developing a plurality of signals representing the retrieved machine states;

a pipeline register coupled to said RAM array to receive said retrieved machine states signals, for latching the state of each of said retrieved machine states, and for developing a plurality of signals representing the latched machine states; and

fourth coupling means connected to said data register of said serial protocol register and to said second multiplexer, said fourth coupling means for selectively coupling to said data register of said serial protocol register at least some of said selected one of said first and second series of RAM array addresses signals, wherein said serial protocol register develops therefrom at least one serial format data word, and wherein said serial protocol register develops said delayed serial bit stream signal to further represent said serial format data word.

6. A registered RAM system for receiving an externally generated serial bit stream signal that includes both a command portion representing in serial format a command and a data words portion representing in serial format both an initial address and a plurality of machine states, for receiving an externally generated plurality of singals representing a first series of RAM array addresses, for receiving an externally generated serial bit stream clocking signal, and for receiving an externally generated command/data signal, said registered RAM system comprising in combination:

a serial protocol register for receiving the serial bit stream signal, for converting from serial to parallel format the command, the initial address, and at least some of said machine states, for developing a plurality of signals representing the parallel format initial address and parallel format machine states, for developing a first counter clocking signal, and for developing a counter loading signal, said serial protocol register including,

first coupling means,

a command register having a clock input coupled by said first coupling means to receive the serial bit stream clocking signal, a serial data input coupled to receive the command portion of said serial bit stream signal, a serial data output at which said command register develops a signal representing said command portion of said serial bit stream signal delayed a predetermined number of cycles of said serial bit stream signal clocking signal, and a predetermined number of parallel data outputs at which said command register develops a plurality of signals representing said parallel format command,

a commamnd decoder having a predetermined number of parallel data inputs coupled to said command register to receive at least a predetermined number of said parallel format command signals, said command decoder for developing said counter loading signal,

second coupling means,

a data register having a clock input coupled by said second coupling means to receive said serial bit stream clocking signal, a serial data input coupled to receive the data words portion of said serial bit stream signal, a serial data output at which said data register develops a signal representing at least a portion of said data word portion of said serial bit stream signal delayed a predetermined number of cycles of said serial bit stream signal clocking singal, and a predetermined number of parallel data outputs at which said data register develops a plurality of signals representing said parallel format initial address and said parallel format machine states,

third coupling means, and

a first multiplexer having a first data input coupled by said third coupling means to said command register serial data output to receive said delayed command portion signal, a second input coupled to said data register serial data output to receive said delayed data word portion signal, a control input coupled to receive the command/data signal, and a data output at which said first multiplexer develops a delayed serial bit stream signal representing a combination of at least said delayed command portion and said delayed data word portion;

an initialization counter connected to said serial protocol register to receive said counter loading signal and to receive said parallel format initial address signals at a time delineated by said counter loading signal and coupled to said serial protocol register to receive said first counter clocking signal, said initialization counter being clocked by said first counter clocking signal to develop a plurality of signals representing a second series of RAM array addresses;

a second multiplexer including a first set of data inputs to receive the first series of RAM array addresses signals, a second set of data inputs connected to said initialization counter to receive said second series of RAM array addresses signals, and a set of data outputs at which said second multiplexer develops a plurality of signals representing a selected one of said first and said second series or RAM array addresses signals;

a RAM array including a plurality of storage locations, said RAM array coupled to said second multiplexer to receive said selected one of said first and second series of RAM array addresses signals and coupled to said serial protocol register to receive said parallel format machine states signals, said RAM array for storing said parallel format machine states each at a respective one of said storage locations addressed by a respective one of said second series of RAM array addresses to initialize said RAM array, for retrieving at least some of the stored machine states each stored at one of said storage locations addressed by a respective one of said first series of RAM array addresses, and for developing a plurality of signals representing the retrieved machine states;

a pipeline register coupled to said RAM array to receive said retrieved machine states signals, for latching the state of each of said retrieved machine states, and for developing a plurality of signals representing the latched machine states; and

fourth coupling means connected to said data register of said serial protocol register and to said RAM array, said fourth coupling means for selectively coupling to said data register of said serial protocol register at least some of said retrieved machine states signals, wherein said serial protocol register develops therefrom at least one serial format data word, and wherein said serial protocol register develops said delayed serial bit stream signal to further represent said serial format data word.

7. A registered RAM system for receiving an externally generated serial bit stream signal that includes both a command portion representing in serial format a command and a data words portion representing in serial format both an initial address and a plurality of machine states, for receiving an externally generated plurality of signals representing a first series of RAM array addresses, for receiving an externally generated serial bit stream clocking signal, and for receiving an externally generated command/data signal, said registered RAM system comprising in combination:

a serial protocol register for receiving the serial bit stream signal, for converting from serial to parallel format the command, the initial address, and at least some of said machine states, for developing a plurality of signals representing the parallel format initial address and parallel format machine states, for developing a first counter clocking signal, and for developing a counter loading signal, said serial protocol register including,

first coupling means,

a command register having a clock input coupled by said first coupling means to receive the serial bit stream clocking signal, a serial data input coupled to receive the command portion of said serial bit stream signal, a serial data output at which said command register develops a signal representing said command portion of said serial bit stream signal delayed a predetermined number of cycles of said serial bit stream signal clocking signal, and a predetermined number of parallel data outputs at which said command register develops a plurality of signals representing said parallel format command,

a command decoder having a predetermined number of parallel data inputs coupled to said command register to receive at least a predetermined number of said parallel format command signals, said command decoder for developing said counter loading signal,

second coupling means,

a data register having a clock input coupled by said second coupling means to receive said serial bit stream clocking signal, a serial data input coupled to receive the data words portion of said serial bit stream signal, a serial data output at which said data register develops a signal representing at least a portion of said data word portion of said serial bit stream signal delayed a predetermined number of cycles of said serial bit stream signal clocking signal, and a predetermined number of parallel data outputs at which said data register develops a plurality of signals representing said parallel format initial address and said parallel format machine states,

third coupling means, and

a first multiplexer having a first data input coupled by said third coupling means to said command register serial data output to receive said delayed command portion signal, a second input coupled to said data register serial data output to receive said delayed data word portion signal, a control input coupled to receive the command/data signal, and a data output at which said first multiplexer develops a delayed serial bit stream signal representing a combination of at least said delayed command portion and said delayed data word portion;

p1 an initialization counter connected to said serial protocol register to receive said counter loading signal and to receive said parallel format initial address signals at a time delineated by said counter loading signal and coupled to said serial protocol register to receive said first counter clocking signal, said initialization counter being clocked said first counter clocking signal to develop a plurality of signals representing a second series of RAM array addresses;

a second multiplexer including a first set of data inputs to receive the first series of RAM array addresses signals, a second set of data inputs connected to said initialization counter to receive said second series of RAM array addresses signals, and a set of data outputs at which said second multiplexer develops a plurality of signals representing a selected one of said first and said second series of RAM array addresses signals;

a RAM array including a plurality of storage locations, said RAM array coupled to said second multiplexer to receive said selected one of said first and second series of RAM array addresses signals and coupled to said serial protocol register to receive said parallel format machine states signals, said RAM array for storing said parallel format machine states each at a respective one of said storage locations addressed by a respective one of said second series of RAM array addresses to initialize said RAM array, for retrieving at least some of the stored machine states each stored at one of said storage locations addressed by a respective one of said first series of RAM array addresses, and for developing a pluralilty of signals representing the retrieved machine states;

a pipeline register coupled to said RAM array to receive said retrieved machine states signals, for latching the state of each of said retrieved, machine states, and for developing a plurality of signals representing the latched machine states; and

fourth coupling means connected to said data register of said serial protocol register and to said pipeline register, said fourth coupling means for selectively coupling to said data register of said serial protocol register at least some of said latched machine states signals, wherein said serial protocol register develops therefrom at least one serial format data word, and wherein said serial protocol register develops said delayed serial bit stream signal to further represent said serial format data word.