Digital computer code word identification system

• US 5,099,516 A
• Filed: 06/12/1989
• Issued: 03/24/1992
• Est. Priority Date: 06/12/1989
• Status: Expired due to Term

• Current Assignee: Dell USA LP (Dell Technologies Inc.)
• Original Assignee: Dell Corporate Services Corporation (Dell Technologies Inc.)
• Inventors: Durkin, Michael D., Stewart, Greg N.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Fagan, Matthew C.
• Application Number:
  US07/365,334
• Time in Patent Office: 1,016 Days
• Field of Search: 364/200, 364/900, 380/4, 340/824.34
• US Class Current: 726/2
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A digital computer system has a central processor unit (CPU). A computer program, entered into the digital computer system for execution thereof, has a program code word embedded at an arbitrary location therein. An addressable programmable array of logic (PAL) is operatively connected to the CPU for receiving a READ signal originated by the CPU at the address of the PAL, the PAL being programmed to output a portion of a preset array code word in a response to the READ signal, and to output the remainder of the array code word in segments in response to subsequent READ signals at the same address. A data bus, connected to receive and transmit the portion and remainders of the array code word to the CPU for comparison with the program code word. The program code word and the array code word are compared and, if identical permit use of the program and do not permit use when the program code word and the array code word are not identical.

Claims

1. A method of identifying a digital computer system having a central processor unit (CPU) and a memory, comprising the steps of:

(a) embedding a program code word in a computer program;

(b) entering the computer program by way of the CPU into the memory of the digital computer system;

(c) programming an addressable logic array, external to the system, with a preset array code word, the addressable logic array comprising a programmable array of logic (PAL);

(d) reading a portion of the preset array code word by way of the CPU at an address of the logic array;

(e) subsequently reading the remaining portion of the preset array code word by way of the CPU at the same address of the logic array;

(f) assembling the preset array code word with the portion and the remaining portion by way of the CPU;

(g) comparing the program code word with the preset array code word by way of the CPU; and

(h) causing the CPU to refuse to execute the program if the program code word and the preset array code word are not identical, and executing the program if the program code word and the preset array code word are identical.

2. The method of claim 1 wherein the step of programming comprises opening desired fuses in the PAL.

3. The method of claim 2, further comprising the step of counting the portion and the remaining portion of the array code word, a count thereby identifying the portion and the remaining portion of the CPU.

4. The method of claim 3 wherein the program code word and the array code word each comprise twenty-four bits.

5. The method of claim 4 wherein the portion of the array code word comprises four bits, in the step of subsequently reading the remaining portion comprises reading five subsequent times at the same address of the logic array, providing four-bit segments each time.

6. A digital computer system, including a central processor unit (CPU) and a memory, comprising:

(a) a computer program stored in the memory of the digital computer system for execution thereof, the program having a program code word embedded at an arbitrary location therein;

(b) an addressable identification logic array, operatively connected to the CPU for receiving a read signal originated by the CPU at an address of the logic array, the logic array being programmed to output a portion of a preset array code word in response to the read signal at the address of the logic array and the remaining portion of the array code word in response to at least one subsequent read signal at the same address of the logic array, the logic array comprising a counter for counting the read signal and the at least one subsequent read signal to identify the portion and the remaining portion of the array code word to enable the logic array to output the portion and the remaining portion in the proper sequence; and

(c) a data bus, connected to the logic array and the CPU for transmitting the portion and the remaining portion of the array code word to the CPU for comparison with the programmed code word by the CPU to permit execution of the program by the CPU when the program code word and the array code word are identical, and to not permit execution of the program when the program code word and the array code word are not identical.

7. The system of claim 6 wherein the logic array further comprises a programmable array of logic (PAL), programmed externally of the system by opening selected fuses to form the logic array.

8. The system of claim 7 wherein the PAL comprises a security fuse, opened and positioned in the logic array to prevent identifying the opened fuses.

9. The system of claim 8 wherein the program code word and the array code word each comprise twenty-four bits.

10. The system of claim 9 wherein the portion of the array code word comprises four bits, and the at least one subsequent read signal includes five subsequent read signals, causing the PAL to output four-bit segments for each subsequent read signal.

11. The system of claim 10 wherein the PAL further comprises a first plurality of input pins, selectively tied to high and low voltages to encode a system model type, and to transfer the encoded system model type to the data bus at a first predetermined count of the counter.

12. The system of claim 11 wherein the PAL further comprises a second plurality of input pins, selectively tied to high and low voltages to encode a number of a present system revision, and to transfer the number to the data bus at a second predetermined count of the counter.