Semiconductor AC switch

• US 5,100,821 A
• Filed: 12/24/1990
• Issued: 03/31/1992
• Est. Priority Date: 04/24/1989
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Fay, Gary V.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): TRINH, LOC
• Application Number:
  US07/632,773
• Time in Patent Office: 463 Days
• Field of Search: 437/47, 437/60, 357/40, 357/41, 357/42, 357/51, 429/7, 307/66, 29/263.5
• US Class Current: 438/19
• CPC Class Codes: H03K 17/6874 in a symmetrical configuration
• CPC Class Codes: H03K 17/785 controlling field-effect transistor switches
• CPC Class Codes: Y10T 29/49115 including coating or impregnating

Abstract

An improved semiconductor AC switch is described having internal bias generation for the power MOSFET switches and isolated control input. Dual power MOSFETS with substrate diodes are connected in series between source and load. DC gate bias for the MOSFETS is derived from an internal power supply containing energy storage which charges from the line, typically every half cycle. The gates of the power MOSFETS are tied to the internal bias generator through a voltage divider network containing a variable resistance controlled by an optical input signal. The internal energy storage may be a capacitor or solid state battery, preferably a monolithic thick or thin film battery. No transformers or external control bias generators are required and the resulting switch is particularly simple and compact.

Claims

1. A method for forming a semiconductor device having thereon an integral battery, comprising:

providing a substrate having one or more semiconductor elements formed in a first surface thereof;

covering the first surface of the substrate with a protective dielectric planarization layer having a smooth upper surface and of a material for protecting underlying semiconductor elements from an overlying battery; and

providing an integral battery having a positive plate and a negative plate separated by a solid electrolyte, wherein the integral battery is formed on the protective dielectric planarization layer and both the positive plate and the negative plate are electrically coupled to the semiconductor elements.

2. The method of claim 1 further comprising, providing at least first and second electrical contacts extending through the planzarization layer for coupling the integral battery to the semiconductor elements.

3. The method of claim 1 wherein the step of providing an integral battery comprises providing multiple superposed battery layers electrically in series, wherein a first, lowest layer is electrically connected to the first contact and a last, uppermost, layer is electrically connected to the second contact.

4. The method of claim 3 wherein the step of providing an integral battery comprises providing an integral battery which, not including the first and last layers, has intervening multiple superposed layers that do not overlie the first and second contacts.

5. The method of claim wherein the step of providing an integral battery comprises providing an integral battery overlying field effect transistors formed in the substrate and separated therefrom by the protective dielectric planarization layer.

6. A method for providing a semiconductor device with integral battery means, comprising:

providing a semiconductor substrate containing therein at least one semiconductor transistor region and having an uneven upper surface, wherein the at least one semiconductor transistor region is located in the upper surface;

forming patterned conductive elements on the upper surface of the semiconductor substrate, wherein the conductive elements couple to the at least one semiconductor transistor region;

forming on the substrate and the patterned conductive elements a protective dielectric planarization layer having a smooth upper surface for receiving an integral battery and which separates the underlying at least one semiconductor transistor region and patterned conductive elements from materials used to form the overlying integral battery; and

forming the integral battery on the upper surface of the protective dielectric planarization layer at least partly above the at least one semiconductor transistor region.

7. The method of claim 6 further comprising forming a polycrystalline semiconductor layer over the substrate and coupling an electrode of the integral battery to the polycrystalline semiconductor layer.

8. The method of claim 6 wherein the steps of providing the substrate and forming the integral battery comprise forming at least one semiconductor transistor region completely underlying the integral battery.

9. The method of claim 6 further comprising forming a first electrical contact for an upper plate of the integral battery which first electrical contact is laterally outside an outline formed by a projection of stacked plates of the battery viewed looking toward the substrate.

10. The method of claim 9 further comprising forming a second electrical contact for a lower plate of the integral battery which second electrical contact is laterally outside an outlet formed by a projection of stacked plates of the battery viewed looking toward the substrate.

11. The method of claim 10 wherein the steps of forming the first and second electrical contacts comprises forming first and second electrical contacts extending to the substrate.