Variable delay line phase-locked loop circuit synchronization system

• US 5,101,117 A
• Filed: 02/22/1991
• Issued: 03/31/1992
• Est. Priority Date: 02/17/1988
• Status: Expired due to Term

• Current Assignee: MIPS Technologies Incorporated (Wave Computing, Inc.)
• Original Assignee: Mips Computer Systems, Inc. (Graphics Properties Holdings, Inc.)
• Inventors: Johnson, Mark G., Hudson, Edwin L.
• Primary Examiner(s): Callahan, Timothy P.
• Application Number:
  US07/659,526
• Time in Patent Office: 403 Days
• Field of Search: 307/269, 307/262, 307/606, 307/594, 307/597, 307/480, 328/55, 328/63, 328/72, 328/155, 328/133, 377/47, 377/78, 377/79, 377/52
• US Class Current: 327/149
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03L 7/0812 and where no voltage or current controlled oscillator is used

Abstract

A system for synchronizing the operation of a CPU and coprocessor operating from a common clock signal includes a first voltage controlled delay line connected to receive the clock signal and delay it by a fixed time interval before supplying it to one of the CPU or coprocessor. A second voltage controlled delay line is connected to receive the clock signal and delay it by an adjustable time interval before supplying it to the other of the CPU or coprocessor. The time interval of the second delay line is determined by the potential of a control signal generated from a phase locked loop circuit coupled to the output terminals of the CPU and coprocessor.

Claims

1. A system for synchronizing a first and a second circuit receiving a common clock signal, and in response to an active transition of said clock signal, said first circuit producing an active transition in a first output signal and said second circuit producing an active transition in a second output signal the synchronizing system comprising:

first delay means coupled to the first circuit and receiving the common clock signal for delaying the common clock signal by a selected interval before supplying the common clock signal to the first circuit;

second delay line means coupled to the second circuit and receiving the common clock signal for delaying the common clock signal by an adjustable interval in response to a control signal before supplying the common clock signal to the second circuit; and

phase detection means coupled to said first and second circuits for detection of the active transition of said second output signal relative to said first output signal during a cycle of said common clock signal, said phase detection means generating a control signal in response to the respective detections of the active transitions in said first and second output signals, said control signal having a voltage potential determined by the relative detections of the active transitions of the first and second output signals, the phase detection means comprising an edge-triggered flip-flop circuit for detecting which of the active transitions of said first and second output signals occurred earlier and means for averaging the control signal over time before supplying the control signal to the second delay means.

2. A system as in claim 1 wherein the phase detection means further comprises means for changing the control signal by a fixed magnitude on each cycle, the change being in a first direction for an earlier detection of the first output signal active transition than that of the second output signal, the change being in a second direction for an earlier detection of the second output signal active transition than that of the first output signal.

3. The system as in claim 1 wherein:

the selected interval of the first delay line is mid-range of a selected interval range.

4. A system as in claim 1 wherein the second delay line means comprises a voltage-controlled delay line for delaying the clock signal by a time related to the potential of the control signal.

5. A system as in claim 4 wherein the second voltage-controlled delay line includes at least one stage comprising:

an inverter having an input terminal connected to receive the clock signal and having an output terminal;

a resistor-capacitor network having a variable time constant, the network connected between the output terminal and a fixed potential; and

control means connected to the network and connected to receive the control signal and in response vary the time constant.

6. The system as in claim 5 wherein the network comprises:

a capacitor having a first electrode connected to the fixed potential; and

a transistor having a first electrode connected to the output terminal of the inverter, a second electrode to a second electrode of the capacitor, and a control electrode connected to receive the control signal.

7. A system as in claim 6 wherein the voltage-controlled delay line comprises a plurality of stages.

8. A system as in claim 7 wherein the delay line comprises an even number of stages.

9. A system as in claim 1 wherein the averaging means comprises:

a first current source switchably connected by a first switch between a storage capacitor and an upper potential source;

a second current source switchable connected by a second switch between the storage capacitor and a lower potential source; and

switching means responsive to the control signal for controlling the first and second current sources.

10. A system as in claim 9 wherein the switching means comprises:

a pulse generator for supplying pulses;

a first gate connected to receive the pulses and the control signal and having a first output coupled to control the first switch; and

a second gate connected to receive the pulses and a complementary control signal and having a second output coupled to the second switch.

11. A system as in claim 1 wherein the first circuit comprises a microprocessor and the second circuit comprises a coprocessor.

12. The system of claim 1 in which the averaging means comprises:

a first current source switchably connected by a first switch between a storage capacitor and an upper potential source,

a second current source switchably connected by a second switch between the storage capacitor and a lower power potential, and

switching means responsive to the control signal for controlling the first and second current sources,

the averaging means connected to receive the control signal and average the control signal over time before supplying the control signal to the second delay line means.

13. A system for synchronizing a first and a second circuit receiving a common clock signal, and in response to an active transition of said clock signal, said first circuit producing an active transition in a first output signal and said second circuit producing an active transition in a second output signal the synchronizing system comprising:

first delay means coupled to the first circuit and receiving the common clock signal for delaying the common clock signal by a selected interval before supplying the common clock signal to the first circuit;

second delay line means coupled to the second circuit and receiving the common clock signal for delaying the common clock signal by an adjustable interval in response to a control signal before supplying the common clock signal to the second circuit; and

phase detection means coupled to said first and second circuits for detection of the active transition of said second output signal relative to said first output signal during a cycle of said common clock signal, said phase detection means generating a control signal in response to the respective detections of the active transitions in said first and second output signals, the phase detection means comprising means for changing the control signal by a fixed magnitude on each cycle, the change being in a first direction for an earlier detection of the first output signal active transition than that of the second output signal, the change being in a second direction for an earlier detection of the second output signal active transition than that of the first output signal, the phase detection means further comprising means for averaging the control signal over time before supplying the control signal to the second delay means.

14. A system as in claim 13 wherein the means for detecting further comprises an edge-triggered flip-flop circuit for detecting which of the active transitions of said first and second output signals occurred earlier.

15. The system of claim 13 in which the averaging means comprises:

a first current source switchably connected by a first switch between a storage capacitor and an upper potential source,

a second current source switchably connected by a second switch between the storage capacitor and a lower power potential, and

switching means responsive to the control signal for controlling the first and second current sources,

the averaging means connected to receive the control signal and average the control signal over time before supplying the control signal to the second delay line means.

16. A system for synchronizing a first and a second circuit receiving a common clock signal, and in response to an active transition of said clock signal, said first circuit producing an active transition in a first output signal and said second circuit producing an active transition in a second output signal the synchronizing system comprising:

first delay means coupled to the first circuit and receiving the common clock signal for delaying the common clock signal by a selected interval before supplying the common clock signal to the first circuit;

second delay line means coupled to the second circuit and receiving the common clock signal for delaying the common clock signal by an adjustable interval in response to a control signal before supplying the common clock signal to the second circuit; and

phase detection means coupled to said first and second circuits for detection of the active transition of said second output signal relative to said first output signal said phase detection means generating a control signal in response to the respective detections of the active transitions in said first and second output signals, said control signal having a voltage potential determined by the relative detections of the active transitions of the first and second output signals, the phase detection means including averaging means, the averaging means comprising;

a first current source switchably connected by a first switch between a storage capacitor and an upper potential source,

a second current source switchable connected by a second switch between the storage capacitor and a lower potential source; and

switching means responsive to the control signal for controlling the first and second current sources,

the averaging means connected to receive the control signal and average the control signal over time before supplying the control signal to the second delay line means.