Pin electronics test circuit for IC device testing

• US 5,101,153 A
• Filed: 01/09/1991
• Issued: 03/31/1992
• Est. Priority Date: 01/09/1991
• Status: Expired due to Fees

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Morong, William H. III
• Primary Examiner(s): Karlsen, Ernest F.
• Application Number:
  US07/639,823
• Time in Patent Office: 447 Days
• Field of Search: 324/158 R, 324/73.1, 324/158 F, 371/22.1, 371/22.6, 371/25.1, 371/27
• US Class Current: 324/537
• CPC Class Codes: G01R 31/2844 using test interfaces, e.g. adapters, test boxes, switches, PIN drivers G01R31/2889 takes precedence
• CPC Class Codes: G01R 31/31924 Voltage or current aspects, e.g. driver, receiver

Abstract

A pin electronics test circuit applies test signals at a pin of an ECL integrated circuit (IC) device under test (DUT) and senses and measures pin signals received from a pin of the DUT. The pin electronics test circuit incorporates test signal first and second electrical paths (TL1, TL2) (TL11, TL12) with respective test connect and disconnect first and second nodes (n1)(n2). First and second termination circuits (RL1, A1)(RL2,A2), first and second DC test signal generators (A1 etc.) (A2 etc.) for forcing DC test signal voltages and currents, AC test signal generator (I_HI, I_LO etc.) for switching between and driving AC test signals of high and low potential levels, and pin signal sensing and measuring circuits (CR1, 8CR2) are all contained on a single pin electronics card (PEC) (54) or formed as a single unit for a pin or complementary pair of pins of the DUT. Electronic switches including FET switches (S1,S3,S4,S5,S6,S7) and current sink switches (S2,S8,S9) permit rapid reconfiguration of the components of the pin electronic circuit with respect to the pair of test signal paths for testing in each of the different required testing modes for single ended, complementary output, and bus type ECL devices. The impedance discontinuities caused by electromechanical relays are eliminated permitting controlled impedance test signal paths. The pin electronics test circuit unit permits comprehensive testing including DC parameter tests, AC parameter tests, and AC or dynamic function tests.

Claims

1. Pin electronics test means for applying test signals at a pin of an integrated circuit (IC) device under test (DUT) and for sensing pin signals received from a pin of the DUT, said pin electronics test means comprising:

test signal first electrical path means having a test connect and disconnect first node, said first electrical path means defining a test signal path between said first node and a first path coupling for electrical connection to a pin of a DUT;

a first terminating resistor coupled to said first node;

first forcing amplifier means having an output coupled to said first terminating resistor, said forcing amplifier means having a first control input for applying a controlling signal, and a second feedback input;

a first feedback circuit coupled between the forcing amplifier means output and said feedback input for applying a steady state first terminating voltage source in series with the first terminating resistor;

said first terminating resistor, first feedback circuit, and first terminating voltage source forming a first terminating means providing substantially the function of a transmission line parallel termination for the first electrical path means for receiving pin signals from a pin of a DUT;

first electronic switch means coupled in the first feedback circuit for electrically connecting and disconnecting the first terminating means with respect to said first node;

AC test signal generating means coupled to said first node for generating and switching between AC test signals comprising data test signals of logic high and low potential levels and for driving said AC test signals on the first electrical path means for stimulating a pin of a DUT;

second electronic switch means coupled for electrically connecting and disconnecting the AC test signal generating means with respect to said first node;

at least a second feedback circuit coupled between the first node and said feedback input of the forcing amplifier means;

said second feedback circuit and first forcing amplifier means providing a first DC test signal generating means coupled to said first node for generating steady state DC test signals and forcing a DC test signal at a pin of a DUT;

third electronic switch means coupled in the second feedback circuit for electrically connecting and disconnecting the first DC test signal generating means with respect to said first node;

and measuring means coupled to said test connect and disconnect first node for sensing and measuring pin signals from a pin of a DUT.

2. The pin electronics test means of claim 1 wherein the second feedback circuit is coupled between a pin of a DUT and the feedback input of the forcing amplifier means, said first DC test signal generating means providing a steady state voltage generating means for forcing a steady state voltage DC test signal at a pin of a DUT.

3. The pin electronics test circuit of claim 2 wherein the first DC test signal generating means comprises a third feedback circuit coupled to provide a steady state current generating means for forcing a steady state current DC test signal at a pin of a DUT;

and fourth electronic switch means coupled in the third feedback circuit for electrically connecting and disconnecting the steady state current generating means with respect to said first node.

4. The pin electronics test means of claim 3 further comprising:

test Signal second electrical path means having a test connect and disconnect second node, said second electrical path means defining a test signal path between said second node and a second path coupling for electrical connection to a pin of a DUT;

second terminating means comprising a second terminating resistor and second terminating voltage source coupled in series to said second node providing substantially the function of a transmission line parallel termination for the second electrical path means for receiving pin signals from a pin of a DUT;

and fifth electronic switch means coupled for electrically connecting and disconnecting the second terminating means with respect to said second node.

5. The pin electronics test means of claim 4 further comprising:

second DC test signal generating means coupled to said second node for generating DC test signals comprising steady state voltage generating means for generating a steady state voltage DC test signal on the second electrical path means and forcing said voltage DC test signal at a pin of a DUT, and steady state current generating means for generating a steady state current DC test signal on the second electrical path means and forcing said current DC test signal at a pin of a DUT;

sixth electronic switch means coupled for electrically connecting and disconnecting the steady state voltage generating means with respect to said second node;

seventh electronic switch means coupled for electrically connecting and disconnecting the steady state current generating means with respect to said second node;

said measuring means being coupled to said test connect and disconnect second node for sensing and measuring pin signals from a pin of a DUT.

6. The pin electronics test means of claim 4 wherein the AC test signal generating means comprises a complementary output signal generating means having complementary first and second outputs for delivering respective logic high and low potential level data test signals in opposite phase, said complementary output signal generating means first output being coupled to the first node, said second electronic switch means electrically connecting and disconnecting said first output with respect to said first node, said complementary output signal generating means second output being coupled to the second node, and an eighth electronic switch means coupled for electrically connecting and disconnecting said second output with respect to said second node.

7. The pin electronics test means of claim 6 wherein the first path coupling of the first electrical path means and the second path coupling of the second electrical path means are electrically connected to different pins of a DUT for testing differential output ECL type DUT'"'"'s in a complementary output mode.

8. The pin electronics test of claim 7 wherein the second and eighth electronic switch means are closed connecting the respective first and second complementary outputs of the AC test signal generating means to the respective first and second nodes.

9. The pin electronics test means of claim 4 wherein the first path coupling of the first electrical path means and the second path coupling of the second electrical path means are electrically connected to the same pin of a DUT for testing bus type DUT'"'"'s in the bus mode.

10. The pin electronics test means of claim 9 wherein the second electronic switch means is closed connecting the AC test signal generating means to the first node and wherein the fifth electronic switch means is closed connecting the second terminating means to the second node.

11. The pin electronics test means of claim 4 wherein the first and second electrical path means, the first and second terminating means, AC test signal generating means, first and second DC signal generating means, and measuring means are formed on a single pin electronics card or board (PEC).

12. The pin electronics test means of claim 10 further comprising:

a DUT board having pin contacts for indexing a DUT for testing, said DUT board being formed with a first electrical path means continuation to a pin contact and a second electrical path means continuation to a pin contact;

and an interconnect interface electrically connecting the PEC and DUT board with electrical continuity between the first electrical path means and first electrical path means continuation and between the second electrical path means and second electrical path means continuation.

13. The pin electronics test means of claim 12 wherein the first and second electrical path means continuations on the DUT board are coupled to the same pin contact for testing bus type DUT'"'"'s in the bus mode.

14. The pin electronics test means of claim 12 wherein the first and second electrical path means continuations are connected to different pin contacts for testing differential type ECL devices in the complementary output mode.

15. The pin electronics test means of claim 1 wherein the AC test signal generating means comprises a three level current switch means coupled to said first node for alternatively establishing a first high level current through the first terminating resistor for a logic high potential level data test signal at the first node, establishing a second low level current through the first terminating resistor for a logic low potential level data test signal at the first node, and electrically turning off a current through the terminating resistor below a threshold level for disconnecting the AC signal generating means from the first node.

16. The pin electronics test means of claim 1 wherein the AC test signal generating means comprises:

a first current source coupled to said first node through a disconnect diode element oriented for conduction of current to the first node, said first current source being coupled between a high potential level power rail and said disconnect diode element for sourcing current through the terminating resistor and establishing a logic high potential level data test signal at said first node; and

a logic level current sink switch coupled between the anode lead of said disconnect diode element and a low potential level power rail for diverting a first fractional portion of current from the first current source away from the disconnect diode element and terminating resistor for establishing a logic low potential level data test signal at said first node when the logic level current sink switch is closed;

and wherein the second electronic switch means comprises a disable current sink switch coupled between the anode lead of said disconnect diode element and a low potential level power rail for diverting a second fractional portion of current from the first current source away from the disconnect diode element causing the potential drop across the disconnect diode element to fall below the diode element threshold voltage level for disconnecting the AC test signal generating means from the first node.

17. The pin electronics test means of claim 6 wherein the AC test signal generating means comprises:

a first current source coupled to the first node of the first electrical path means through a first disconnect diode element oriented for conduction to the first node, said first current source being coupled between a high potential level power rail and said first disconnect diode element for sourcing current through the first terminating resistor for establishing a logic high potential level data test signal at said first node;

a second current source coupled to the second node of the second electrical path means through a second disconnect diode element oriented for conduction to the second node, said second current source being coupled between a high potential level power rail and said second disconnect diode element for sourcing current through the second terminating resistor and establishing a logic high potential level data test signal at said second node;

and a differential logic level current sink switch having complementary first and second current switch paths, said first current switch path being coupled between the anode lead of the first disconnect diode element and a low potential level power rail for diverting a first fractional portion of current from the first current source away from the first disconnect diode element and first terminating resistor for establishing a logic low potential level data test signal at said first node when the first current switch path is closed, said second current switch path being coupled between the anode lead of the second disconnect diode element and a low potential level power rail for diverting a first fractional portion of current from the second current source away from the second disconnect diode element and second terminating resistor for establishing a logic low potential level data test signal at said second node when the second current switch path is closed, said first and second current switch paths being opened and closed in opposite phase.

18. The pin electronics test means of claim 17 wherein the second electronic switch means comprises a first disable current sink switch coupled between the anode lead of said first disconnect diode element and a low potential level power rail for diverting a second fractional portion of current from the first current source away from the first disconnect diode element causing the potential drop across the first disconnect diode element to fall below the diode threshold voltage level for disconnecting the AC test signal generating means from the first node.

19. The pin electronics test means of claim 18 further comprising a second disable current sink switch coupled between the anode lead of said second disconnect diode element and a low potential level power rail for diverting a second fractional portion of current from the second current source away from the second disconnect diode element causing the potential drop across the second disconnect diode element to fall below the diode threshold voltage level for disconnecting the AC test signal generating means from the second node, said second disable current sink switch comprising the eighth electronic switch.

20. The pin electronics test means of claim 3 wherein the first forcing amplifier means and first terminating voltage source comprises a first operational amplifier (op amp) having a controlling voltage signal input, a feedback input, and an output coupled to the terminating resistor.

21. The pin electronics test means of claim 20 wherein the steady state current generating means for forcing a selected current DC test signal at a pin of a DUT comprises said third feedback circuit including a first instrumentation amp having first and second inputs coupled respectively to the ends of the first terminating resistor and an output coupled to the feedback input of the first op amp, said fourth electronic switch means being coupled in the third feedback circuit.

22. The pin electronics test means of claim 21 wherein the first, third and fourth electronic switch means comprise FET switches, and wherein the second electronic switch means comprises a current sink switch.

23. The pin electronics test means of claim 21 further comprising a first decoupling resistor in the second feedback circuit, and a second decoupling resistor in the third feedback circuit.

24. The pin electronics test means of claim 3 wherein the first, third, fourth, fifth, sixth, and seventh electronic switch means comprise FET switches and wherein the second and eighth electronic switch means comprise current sink switches.

25. A pin electronics card or unit (PEC) for applying test signals at a pin of an integrated circuit (IC) device under test (DUT) and for sensing pin signals received from a pin of the DUT, said PEC having motherboard coupling means for coupling to a motherboard of a test head of an IC device tester for receiving test control signals from the tester, and DUT board interconnect coupling means for coupling to a DUT board of the test head for driving and forcing test signals at a pin of a DUT mounted on the DUT board and for sensing and measuring pin signals received from a pin of a DUT mounted on the DUT board, said PEC comprising:

test signal first electrical path means having a test connect and disconnect first node, said first electrical path means defining a test signal path between said first node and a first path coupling coupled to the DUT board interconnect coupling means for electrical connection to a pin of a DUT;

first terminating means comprising a first terminating resistor and first terminating voltage source coupled in series to said first node providing substantially the function of a transmission line parallel termination for the first electrical path means for receiving pin signals from a pin of a DUT;

first electronic switch means for electrically connecting and disconnecting the first terminating means with respect to said first node;

AC test signal generating means coupled to said first node for generating and switching between AC test signals comprising data test signals of logic high and low potential levels and for driving said AC test signals on the first electrical path means for stimulating a pin of a DUT;

second electronic switch means for electrically connecting and disconnecting the AC test signal generating means with respect to said first node;

measuring means coupled to said test connect and disconnect first node for sensing and measuring pin signals from a pin of a DUT;

test signal second electrical path means having a test connect and disconnect second node, said second electrical path means defining a test signal path between said second node and a second path coupling coupled to the DUT board interconnect coupling means for electrical connection to a pin of a DUT;

second terminating means comprising a second terminating resistor and second terminating voltage source coupled in series to said second node providing substantially the function of a transmission line parallel termination for the second electrical path means for receiving pin signals from a pin of a DUT and for providing a bus mode termination;

fifth electronic switch means for electrically connecting and disconnecting the second terminating means with respect to said second node;

said measuring means being coupled to said test connect and disconnect second node for sensing and measuring pin signals from a pin of a DUT.

26. The PEC of claim 25 further comprising:

a DUT board having pin contacts for indexing a DUT for testing, said DUT board being formed with a first electrical path means continuation to a pin contact and a second electrical path means continuation to a pin contact;

said DUT board interconnect coupling means electrically connecting the PEC and DUT board with electrical continuity between the first electrical path means and first electrical path means continuation and between the second electrical path means and second electrical path means continuation.

27. The PEC of claim 26 wherein the first and second electrical path means continuations on the DUT board are coupled to the same pin socket for testing bus type DUT'"'"'s in a bus mode.

28. The PEC of claim 26 wherein the AC test signal generating means comprises a complementary output signal generating means having complementary first and second outputs for delivering respective logic high and low potential level data test signals in opposite phase, said complementary output signal generating means first output being coupled to the first node, said second electronic switch means being coupled for electrically connecting and disconnecting said first output with respect to said first node, said complementary output signal generating means second output being coupled to the second node, and an eighth electronic switch means being coupled for electrically connecting and disconnecting said second output with respect to said second node.

29. The PEC of claim 28 wherein the first and second electrical path means continuations on the DUT board are connected to different pin contacts for testing complementary or differential type ECL devices in a complementary output mode.

30. A pin electronics circuit for applying test signals at a pin of an integrated circuit (IC) device under test (DUT) and for sensing pin signals received from a pin of the DUT, said pin electronics circuit comprising:

first and second test signal electrical path means having respective test connect and disconnect first and second nodes, said first and second electrical path means defining separate test signal paths between the respective first and second nodes and first and second path couplings for electrical connection to at least one pin of a DUT;

first and second terminating means comprising respective first and second terminating resistors and respective first and second terminating voltage sources coupled in series to said first and second nodes providing substantially the function of transmission line parallel terminations for the respective first and second electrical path means for receiving pin signals from at least one pin of a DUT;

first electronic switch means coupled for electrically connecting and disconnecting the first terminating means with respect to said first node;

test signal generating means coupled to said first node for generating and electronically switching between test signals and for applying said test signals on the first electrical path means for stimulating a pin of a DUT;

second electronic switch means coupled for electrically connecting and disconnecting the test signal generating means with respect to said first node;

measuring means coupled to said test connect and disconnect first node for sensing and measuring pin signals from a pin of a DUT;

third electronic switch means coupled for electrically connecting and disconnecting the second terminating means with respect to said second node.

31. The pin electronics test circuit of claim 30 wherein the first path coupling of the first electrical path means and the second path coupling of the second electrical path means are electrically connected to different pins of a DUT for testing differential output ECL type DUTs in a complementary output mode, wherein the test signal generating means is also coupled to the second node, wherein the measuring means is also coupled to said second node for sensing and measuring pin signals from a pin of a DUT, and fourth electronic switch means for electrically connecting and disconnecting the test signal generating means with respect to said second node.

32. The pin electronics test circuit of claim 30 wherein the first path coupling of the first electrical path means and the second path coupling of the second electrical path means are electrically connected to the same pin of a DUT for testing bus type DUT'"'"'s in the bus mode.