Memory access control device which can be formed by a reduced number of LSI's

• US 5,101,338 A
• Filed: 04/27/1989
• Issued: 03/31/1992
• Est. Priority Date: 04/27/1988
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Kitamura, Toyoshi, Fujiwara, Yoshifumi
• Primary Examiner(s): Popek, Joseph A.
• Assistant Examiner(s): WHITFIELD, MICHAEL
• Application Number:
  US07/343,886
• Time in Patent Office: 1,069 Days
• Field of Search: 364/200 MS File, 364/ 900 MS File
• US Class Current: 711/220
• CPC Class Codes: G06F 12/0607 Interleaved addressing

Abstract

In an access control device (30) for use in combination with first through (2×m)-th memory units (m: 2, 3, . . . ) each of which is assigned with at least one of addresses consecutively numbered among the memory units, each of first through m-th arithmetic circuits products, in response to a base address B of the addresses and a preselected distance D, an arithmetic result (B+nD), where n represents one of first through m-th values which are equal to "0", "1", . . . , and "m-1", respectively. A value distributing circuit (36) is preliminarily given the values and distributes the first through the m-th values in response to a distributing control signal. Responsive to the base address and to the preselected distance, a signal producing circuit (39) produces the distributing control signal. A result distributing circuit (43) distributes the arithmetic results of the first through the m-th arithmetic circuits to the first through the (2×m)-th memory units as selected ones of the addresses. The selected addresses are determined by selecting the base address in consideration of the preselected distance left between two adjacent ones of the selected addresses.

Claims

1. A memory access control device for use in a vector processing system in combination with a memory device comprising a plurality of memory units which are 2m in number and are called first through 2m-th memory units by using consecutively increasing memory numbers, where m represents an integer which is greater than one, said first through said 2m-th memory units being connected to first through 2m-th memory ports being assigned at least one of a plurality of memory addresses which consecutively increase in correspondence to said consecutively increasing memory numbers, said memory access control device accessing selected ones of said memory addresses by selecting a base address from said memory addresses and by using a preselected distance between two adjacent ones of said selected ones of the memory addresses and including a base register for holding said base address as a held address and a distance register for holding said preselected distance as a held distance, said memory access control device comprising:

first through m-th arithmetic units, each of which is connected to said base address register and said distance register to calculate an arithmetic result given by a formula (B+nD), where B represents said held address, D represents said held distance, and n represents one of a first value 0 through an m-th value (m-1);

a control section connected to said base address register and said distance register for producing a distribution control signal dependent on said held address and said held distance;

a crossbar circuit having first through said m-th values and connected to said first through said m-th arithmetic units and said control section for distributing said first through said m-th values to said first through said m-th arithmetic units in response to said distribution control signal; and

an arithmetic result distributing circuit connected to said first through said m-th arithmetic units and said first through said 2m-th ports for distributing the arithmetic results calculated by said first through said m-th arithmetic units to said first through said 2m-th ports as said selected ones of the memory addresses by changing n in said formula from said first value up to said m-th value and by changing B to (B+m) when n is changed up to said m-th value if said preselected ones of the memory addresses are greater than said m-th value and are not greater than twice said m-th value.