Computer address modification system using writable mapping and page stores

• US 5,101,339 A
• Filed: 01/23/1989
• Issued: 03/31/1992
• Est. Priority Date: 08/10/1987
• Status: Expired due to Fees

• Current Assignee: Tandon Corporation (TSL Holdings, Inc.)
• Original Assignee: Tandon Corporation (TSL Holdings, Inc.)
• Inventors: Swinton, William G., Taylor, Robert G. Jr., Larsen, Allen J., Fairman, Bruce A.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): MOHAMED, AYNI Y
• Application Number:
  US07/300,560
• Time in Patent Office: 1,163 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/2
• CPC Class Codes: G06F 12/0623 for memory modules
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]

Abstract

A computer system includes a computer address modification system that is advantageously coupled in a bus network to selectively translate memory address data in 16K blocks and provide DMA addresses which may match the 16 K memory address blocks. The modification system includes a mapping RAM selectively providing translated addresses to enable addresses in a 16 megabyte extended address space. The modification system also includes a page register storing for each addressable 16K block of data for each DMA channel a page address within the extended address space.

Claims

1. A computer address modification system comprising:

a writable mapping store having as an input at least a portion of an address signal, and generating a modified address signal in response to said input and to data stored in the mapping store;

a writable page address store having a plurality of storage locations for each of a plurality of direct memory access channels and having as inputs (1) a direct memory access channel indication and (2) a direct memory access memory address signal, and generating a modified direct memory access memory address signal in response to data stored in a storage location corresponding to the indicated direct memory access channel; and

wherein the modified direct memory access memory address signal is generated in response to data stored in a data storage location indicated by the direct memory access memory address signal that is within a plurality of data storage locations corresponding to the indicated direct memory access channel.

2. A computer address modification system according to claim 1 further comprising a hardware interrupt detector circuit receiving a nonmaskable interrupt indication signal and selectively disabling modification of memory addresses in response thereto.

3. A computer address modification system according to claim 1 further comprising a hardware interrupt detector circuit for selectively disabling modification of memory addresses upon detecting an occurrence of an interrupt response.

4. A computer address modification system according to claim 1, further comprising an interrupt detector circuit including a vector type latch for receiving and latching a vector type signal generated by an interrupt controller, and disabling modification of memory addresses received by the system upon receipt of an address matching a latched vector type signal.

5. A computer address modification system according to claim 1, wherein the interrupt detector circuit includes a reset circuit coupled to reset the disabling function of the detector circuit in response to receipt of data at a predetermined I/O address port.

6. A computer address modification system having distinguishable I/O and memory address spaces and comprising:

a multiple part mapping memory, each part storing a plurality of partial extended addresses which define a portion of an address for an addressable location in the memory address space, the mapping memory responding to receipt of at least a portion of a limited address defining an address location within a limited portion of the memory address space by outputting from a storage location corresponding to the received limited address portion of a selected one of the two parts indicated by a selection signal a partial extended address for use in forming an address in the memory address space; and

a control store generating the selection signal in response to selection data stored therein, the selection data being changeable in response to a data transfer in the I/O address space to permit a change in the correspondence between extended addresses and limited addresses by changing the stored selection data, said control store further storing translation enable data that is changeable in response to a data transfer in the I/O address space.

7. A computer address modification system according to claim 6 further comprising:

a multiplexer circuit that is responsive to the translation enable data stored by the control store, to the data output of the selected part of the mapping memory and to the received limited address portion, the multiplexing circuit responding to receipt by the modification system of a partial limited address by outputting the partial limited address when the translation enable data indicates that translation is not enabled and by outputting the partial extended address when the translation enable data indicates that address translation is enabled.

8. A computer address modification system according to claim 7 wherein the control store is a single register having a single I/O address space address location and storing the selection data and the translation enable data each at a different signal bit position therein.

9. A computer address modification system according to claim 6 wherein the control store further stores mapping memory write enable data and further comprising write control circuitry disabling a write access to the mapping memory when the mapping memory write enable data has a state indicating that writing in not enabled.

10. A computer address modification system according to claim 9 further comprising a blocking circuit responsive to a received limited address portion and to the stored translation enable data and blocking the generation of an output address when a received limited address portion defines a location beyond the limited address space while the stored translation enable data indicates that address translation is enabled.

11. A computer address modification system according to claim 6 wherein the control store further stores interrupt revectoring enable data that is changeable in response to a data transfer in the I/O address space and further comprising an interrupt revectoring circuit including an interrupt detection circuit detecting and indicating processing of an interrupt routine, the interrupt revectoring circuit disabling translation of received limited addresses when the stored revectoring enable data indicates that revectoring of interrupt process addresses is enabled while an interrupt routine is being processed.

12. A computer address modification system according to claim 11 having an interrupt acknowledge signal input for receiving an interrupt acknowledge signal generated by a data processing system to acknowledge an interrupt request, a data input for receiving data defining an interrupt vector type that is generated by a data processing system in response to the interrupt acknowledge signal and wherein the interrupt detection circuit includes an interrupt detection flip-flop coupled to be set upon receipt of an interrupt acknowledge signal at the interrupt acknowledge signal input an interrupt vector type latch coupled to latch upon receipt of an interrupt acknowledge signal an interrupt vector type received at the data input, and a comparator coupled to compare a received memory space address with a latched vector type and to generate a vector compare signal for inhibiting mapping of the received address when the received address matches the latched vector type and the interrupt detection flip-flop is set.

13. A computer address modification system according to claim 12 further comprising a nonmaskable interrupt signal input for receiving from a data processing system a signal requesting a nonmaskable interrupt and wherein the comparator further generates the vector compare signal when a nonmaskable interrupt signal is present while a received memory space address represents a predetermined address storing a nonmaskable interrupt vector.

14. A computer address modification system according to claim 13 wherein the interrupt detection flip-flop is reset upon receipt of a data transfer in the I/O address space to an address of the control store with a predetermined portion of the transferred data having a predetermined data store.

15. A computer address modification system according to claim 6, further comprising:

a direct memory access controller;

an I/O controller generating address signals defining a portion of a memory space address which corresponds to an active direct memory access channel, the generated portion being combined into a limited address, the limited address being connected to the mapping memory as any other limited address.

16. A computer address modification system according to claim 15, further comprising:

a page store having a plurality of registers, each corresponding to a direct memory access channel and storing a portion of an address in the memory address space, the page store being operative when a direct memory access channel is active to output a stored address portion from a register corresponding to the active direct memory access channel;

a bus system operative in response to a direct memory access operation to combine the address portion generated by a page store register during a direct memory access into a memory space address.

17. A computer address modifications system according to claim 16, further comprising:

an address storage location having an address in the I/O address space and storing a page store enable signal for selectively enabling the page store, the I/O controller receiving the page store enable signal and inhibiting the generation of the portion of the memory space address that is otherwise generated thereby when a direct memory access is active, and the mapping memory receiving the page store enable signal and inhibiting the outputting of a partial extended address when the page store enable signal is active.

18. A computer address modification system for use in a computer system having a plurality of direct memory access channels and including an addressable system page register for each channel storing a portion of an address that is asserted hen the corresponding channel is active and a page register enable signal is in an inactive state and including an addressable storage location for storing a page register enable signal, the address modification system comprising:

a DMA mode register having a channel enable signal storage location corresponding to each different DMA channel;

a page store including a plurality of DMA page registers for each channel, one of the DMA page registers for each channel being a first page register and being addressable in the same manner as the system page register for the given channel so as to receive and store any data written to the system page register; and

a control circuit responsive to the page register enable signal, to a portion of a computer system address, to direct memory access channel indication signals and to the DMA mode register to disable operation of the page store when the page register enable signal is inactive, to address the page store to provide the contents of a first register as a portion of a system address when a direct memory access channel is active while the page register enable signal is active and the channel enable signal stored by the page store for the active channel is in an inactive state and to address the page store when a direct memory access channel is active while the page register enable signal is active and the channel enable signal stored by the page store for the active channel is in an active state to provide as a portion of a system address the contents of a DMA page register corresponding to the active channel which is selected by a portion of a system address provided by the computer system.