I/O structure for information processing system

• US 5,101,478 A
• Filed: 08/04/1988
• Issued: 03/31/1992
• Est. Priority Date: 06/28/1985
• Status: Expired due to Term

• Current Assignee: Acer, Inc.
• Original Assignee: Wang Laboratories Incorporated
• Inventors: Trottier, Robert R., Fu, Andrew N., Morrison, Peter A., MacDonald, James B., Mahoney, Kevin T., Patel, Bhikoo J., Nash, Robert C., Whipple, David L., Olson, Stephen W., Kibler, Tom R.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): FAGAN, MATTHEW
• Application Number:
  US07/228,768
• Time in Patent Office: 1,335 Days
• Field of Search: 364/200, 364/900
• US Class Current: 710/1
• CPC Class Codes: G06F 13/126 and has means for transferring I/O instructions and statuses between control unit and main processor

Abstract

An I/O structure for use in a digital data processing system of the type in which system components including a processor and a system memory are connected by a system bus. The I/O structure includes a system bus interface connected to the system bus, a synchronous satellite processing unit (SPU) bus connected to the system bus interface, one or more satellite processing units (SPUs) connected to the SPU bus, and peripheral devices attached to the satellite processing units. Each SPU has three main components: control logic including a microprocessor for controlling the SPU, a device adapter specific to the peripheral device for controlling the peripheral device and transferring data between the peripheral device and the SPU, and an interface unit connected to the control logic and the device adapter for providing I/O communications to the SPU bus and responding to I/O communications on the SPU bus. The I/O communications fall into two classes: communications to SPUs and communications to system components. The communications to SPUs all require a single SPU bus cycle; the communications to system components require one or more cycles. The system bus interface translates communications to system components into communications on the system bus and translates communications on the system bus intended for a SPU into communications to SPUs. The SPU bus includes first lines for carrying an I/O command and an identifier for an SPU involved in the communication and second lines for carrying the contents of the communication. In multicycle communications, the I/O command and identifier remain on the first lines for all cycles, but the information on the second lines varies from cycle to cycle.

Claims

1. An I/O subsystem component for coupling a peripheral device to an I/O subsystem of a digital data processing system, the I/O subsystem including one or more I/O subsystem components and a synchronous I/O subsystem bus for carrying I/O communications, which require one or more I/O subsystem bus cycles, and which include I/O subsystem communications that have I/O subsystem components as destinations and I/O system communications that have components of the digital data processing system outside of the I/O subsystem as destinations, the I/O subsystem component comprising:

control means for controlling the I/O subsystem component to originate and provide I/O communications, and responding to an incoming message;

device adapter means coupled to the peripheral device and controlled by the control means for transferring outgoing data from the peripheral device for inclusion in certain of the I/O communications and transferring incoming data intended for the peripheral device to the peripheral device; and

interface means coupled to the I/O subsystem bus, to the control means, and to the device adapter means for responding to the control means when the I/O subsystem component is providing an I/O communication to the I/O subsystem bus by receiving I/O communication information for the I/O communication from at least one of the control means and the device adapter means and outputting the I/O communication to the I/O subsystem bus as required for the I/O communication and responding to the I/O subsystem bus by monitoring I/O communications on the I/O subsystem bus and responding thereto only when the I/O communication is one of the I/O subsystem communications and has the I/O subsystem component as its destination by receiving the I/O communication and providing any incoming message to the control means and any incoming data intended for the device adapter means to the device adapter means.

2. The I/O subsystem component as set forth in claim 1 and wherein:

the I/O subsystem bus includes

a first plurality of lines for carrying an I/O command belonging to the I/O communication during all of the I/O subsystem bus cycles required for the I/O communication;

a second plurality of lines for carrying a target identification which belongs to the I/O communication and which identifies an I/O subsystem component involved in the I/O communication during all of the I/O subsystem bus cycles required for the I/O communication; and

a third plurality of lines which carries other information belonging to the I/O communication; and

when the I/O subsystem component is providing an I/O communication to the I/O subsystem bus, the control means provides the I/O command and the target identification to the interface means, and

the interface means outputs the I/O command to the first plurality of lines and the target identification to the second plurality of lines for all of the I/O subsystem bus cycles required for the I/O communication and outputs the other I/O information as required for the I/O communication to the third plurality of lines; and

when the I/O subsystem component is responding to an I/O communication, the interface means responds to an I/O command belonging to one of the I/O subsystem communications on the first plurality of lines and a target identification specifying the I/O subsystem component on the second plurality of lines by receiving the other information on the third plurality of lines.

3. The I/O subsystem component set forth in claim 1 wherein:

certain of the I/O system communications and certain of the I/O subsystem communications each includes a message; and

when the control means controls the I/O subsystem component to originate and provide one of the certain I/O system communications or the certain I/O subsystem communications, the control means provides a message for inclusion in the provided communication.

4. The I/O subsystem component as set forth in claim 1 and wherein:

the digital data processing system includes memory means which are indirectly coupled to the I/O subsystem bus;

the I/O system communications include an I/O memory write communication which specifies an operation in which data is written from the I/O subsystem component to the memory means and which includes the data to be written and the I/O subsystem communications include an I/O subsystem data return communication which specifies an operation in which data is provided to the I/O subsystem component and which includes the data to be provided;

the control means includes means for specifying a direct memory access operation; and

when the direct memory access operation has been specified and the I/O subsystem component is providing the I/O memory write communication, the device adapter means provides outgoing data to the interface means and when the direct memory access operation has been specified and the I/O subsystem component is responding to the I/O subsystem data return communication, the device adapter means takes incoming data from the interface means.

5. The I/O subsystem component as set forth in claim 4 and wherein:

the I/O memory write communication further includes a memory address of the data to be written;

the interface means includes memory address incrementing means and when the direct memory access operation has been specified, the control means provides a start address for a first one of a sequence of I/O memory write communications and the interface means employs the address incrementing means to provide memory addresses for the remaining I/O memory write communications in the sequence.

6. An I/O subsystem system component of a digital data processing system for transferring data to or from one or more peripheral devices in the digital data processing system, the I/O subsystem system component and other system components being coupled to a system bus which transfers system communications among the I/O subsystem system component and the other system components, the I/O subsystem system component comprising:

a synchronous I/O subsystem bus for transferring a plurality of I/O communications which require one or more I/O subsystem bus cycles, the I/O communications including I/O system communications which have system components as their destinations and I/O subsystem communications which have I/O subsystem components within the I/O subsystem system component as their destinations, the I/O subsystem bus comprising

a first plurality of lines for carrying an I/O command portion of one of the I/O communications, the I/O command portion specifying the one I/O communication during all of the I/O subsystem bus cycles required to transfer the one I/O communication,

a second plurality of lines for carrying, during all of the I/O subsystem bus cycles required to transfer the one I/O communication, a target identification portion of the one I/O communication, the target identification identifying the I/O subsystem component which is the source of the one I/O communication when the one I/O communication is an I/O system communication and identifying the I/O subsystem component which is the destination of the one I/O communication when the one I/O communication is an I/O subsystem communication, and

a third plurality of lines which carries an other information portion of the one I/O communication;

one or more I/O subsystem components, each I/O subsystem component being coupled between a given one of the peripheral devices and the I/O subsystem bus for originating I/O communications and providing the I/O communications to the I/O subsystem bus (at least some of these I/O communications including data from the peripheral device) and for responding only to I/O subsystem communications (at least some of these I/O communications including data to the peripheral device); and

system bus interface means which are coupled between the system bus and the I/O subsystem bus for responding to an I/O system communication, on the I/O subsystem bus, by providing a corresponding system communication on the system bus and for responding to a system communication, on the system bus, specifying an operation to be performed in the I/O subsystem system component by providing a corresponding I/O subsystem communication on the I/O subsystem bus.

7. In a digital data processing system wherein system components are connected to a system bus which carries system communications including system interprocessor communications and includes a busy line for carrying a busy signal which indicates to a system component which is a source of a system communication that the system communication cannot presently be sent, the system components include an I/O subsystem system component including an I/O subsystem bus which carries I/O subsystem communications including I/O subsystem interprocessor communications and which has an IPC not ready line for carrying an IPC not ready signal and a system bus interface connected between the I/O subsystem bus and the system bus which converts system interprocessor communications destined for an I/O subsystem component of the I/O subsystem system component into corresponding I/O subsystem interprocessor communications and I/O subsystem communications destined for other system components into corresponding system communications, an I/O subsystem component (for coupling a

peripheral device to the I/O subsystem bus) comprising:

control means for controlling the I/O subsystem component to originate and provide I/O subsystem communications to the I/O subsystem bus and for responding to incoming messages received in I/O subsystem interprocessor communications and

interface means coupled to the I/O subsystem bus, to the control means, and to the peripheral device for responding to the control means when the I/O subsystem component is providing an I/O subsystem communication to the I/O subsystem bus by receiving I/O subsystem communication information for the I/O subsystem communication and outputting the I/O subsystem communication to the I/O subsystem bus, for responding to the I/O subsystem bus by monitoring I/O subsystem communications on the I/O subsystem bus and responding to an I/O subsystem communication that has the I/O subsystem component as its destination by receiving the I/O subsystem communication and providing any incoming message to the control means and any incoming data intended for the peripheral device to the peripheral device, and for responding to the control means when the I/O subsystem component is unable to respond to a system interprocessor communication destined for the I/O subsystem component by providing the IPC not ready signal to the IPC not ready line,

the system bus interface responding to the IPC not ready signal and to a system interprocessor communication destined for the I/O subsystem component by not converting the system interprocessor communication to a corresponding I/O subsystem interprocessor communication and by outputting the busy signal on the busy line,

whereby the system bus immediately becomes available for any system communication other than a system interprocessor communication destined for the I/O subsystem component.

8. The I/O subsystem component set forth in claim 7 wherein:

the I/O subsystem component is one of a plurality thereof coupled to the I/O subsystem bus, and the I/O subsystem bus includes a separate IPC not ready line for each I/O subsystem component coupled to the I/O subsystem bus;

an I/O subsystem component of the plurality is further a source of certain I/O subsystem interprocessor communications; and

the interface means of an I/O subsystem component of the plurality whose IPC not ready line is carrying the IPC not ready signal and which is not currently a source of an I/O subsystem interprocessor communication remains responsive to an I/O subsystem interprocessor communication whose source is not a system component.

9. An I/O subsystem system component of a digital data processing system for transferring data to or from one or more peripheral devices in the digital data processing system, the I/O subsystem system component and other system components being coupled to a system bus which transfers system communications among the I/O subsystem system component and the other system components, the I/O subsystem system component comprising:

a synchronous I/O subsystem bus for transferring a plurality of I/O communications which require one or more I/O subsystem bus cycles, the I/O communications including I/O system communications which have system components as their destinations and I/O subsystem communications which have I/O subsystem components within the I/O subsystem system component as their destinations,

one or more I/O subsystem components, each I/O subsystem component being coupled between a given one of the peripheral devices and the I/O subsystem bus for originating I/O communications and providing the I/O communications to the I/O subsystem bus (at least some of these I/O communications including data from the peripheral device) and for responding only to I/O subsystem communications (at least some of these I/O communications including data from the peripheral device); and

system bus interface means which are coupled between the system bus and the I/O subsystem bus for responding to an I/O system communication, on the I/O subsystem bus, by providing a corresponding system communication on the system bus and for responding to a system communication, on the system bus, specifying an operation to be performed in the I/O subsystem system component by providing a corresponding I/O subsystem communication on the I/O subsystem bus

and wherein

at least one of the system components is a memory means;

the system communications include a system memory read communication which specifies an operation in which data read from the memory means is returned to the system component which is the source of the memory read communication and a system memory write communication which specifies data and an operation in which the data provided by the system component which is the source of the system memory write communication is written to the memory means;

a system component can perform a lock operation in which system components other than a system component presently having access to the system bus are inhibited from having access thereto and an unlock operation in which other system components are given access to the system bus;

the I/O system communications include a memory test and set communication specifying an operation in which an I/O subsystem component specifies data in the memory means which is to be read and modified;

the I/O subsystem communications include an I/O subsystem data return communication which specifies data and an operation in which the data is returned to an I/O subsystem component; and

the system bus interface means responds to an I/O memory test and set communication by performing the lock operation, producing a system memory read communication on the system bus, then, upon receipt of data from the memory means, producing an I/O subsystem data return communication which includes the received data on the I/O subsystem bus, modifying the received data, producing a system memory write communication which includes the modified data, and performing the unlock operation.

10. Interface apparatus for interfacing an I/O subsystem component of an I/O subsystem system component of a digital data processing system to an I/O subsystem bus, the I/O subsystem system component including at least one I/O subsystem component and the digital data processing system including memory means and other system components which are coupled indirectly to the I/O subsystem bus, the I/O subsystem component being connected to a peripheral device for performing operations as required to transfer data to or from the peripheral device, the operations being specified on the I/O subsystem bus by a plurality of I/O communications which require one or more I/O subsystem bus cycles and which include an I/O memory write communication specifying an operation in which data is transferred from the I/O subsystem component to the memory means, an I/O subsystem message communication specifying an operation in which a message is transferred to an I/O subsystem component, and an I/O subsystem data return communication specifying an operation in which data is returned to an I/O subsystem component, and the I/O subsystem bus including a first plurality of lines for carrying an I/O command specifying one of the I/O communications during all of the I/O subsystem bus cycles required to transfer the specified communication, a second plurality of lines for carrying a target identification identifying an I/O subsystem component involved in the specified communication during all of the I/O subsystem bus cycles required to transfer the specified communication, and a third plurality of lines which carries a memory address during a first I/O subsystem bus cycle and data during a second I/O subsystem bus cycle of the I/O memory write communication, which carries the message during transfer of the I/O subsystem message communication, and which carries data during transfer of the I/O subsystem data return communication, the interface apparatus comprising:

I/O command output means coupled to the first plurality of lines for outputting the I/O command of an I/O communication to the first plurality of lines during all of the I/O subsystem bus cycles required by the I/O subsystem component originating the I/O communication to output the I/O communication;

first output means coupled to the second plurality of lines for outputting an identification of an I/O subsystem component involved in the I/O communication during all I/O subsystem bus cycles required by the I/O subsystem component originating the I/O communication to output the I/O communication;

second output means coupled to the third plurality of lines for outputting a memory address to the third plurality of lines during the first I/O subsystem bus cycle of the memory write communication;

third output means coupled to the third plurality of lines for outputting data to the third plurality of lines during the second I/O subsystem bus cycle of the memory write communication;

target identification receiving means coupled to the second plurality of lines for receiving the target identification of an I/O communication on the I/O subsystem bus and determining whether the received target identification matches an identification of the I/O subsystem component;

I/O command receiving and decoding means coupled to the first plurality of lines for responding to a match detected by the target identification receiving means by receiving and decoding the I/O command of the I/O communication on the first plurality of lines;

message receiving means coupled to the third plurality of lines and responsive to the I/O command decoding means for receiving the message on the third plurality of lines when the target identification and the I/O command indicate that the I/O communication is an I/O subsystem message communication intended for the I/O subsystem component; and

data receiving means coupled to the third plurality of lines and responsive to the I/O command decoding means for receiving data on the third plurality of lines when the target identification and the I/O command indicate that the I/O communication is in I/O subsystem data return communication intended for the I/O subsystem component.

11. The interface apparatus as set forth in claim 10 and wherein:

the data receiving means includes a first data receiving means and a second data receiving means;

the I/O communications further include a plurality of I/O subsystem data return communications including a first data return communication which specifies that data be returned to the first data receiving means and a second data return communication which specifies that data be returned to the second data receiving means; and

when the I/O subsystem component receives a first data return communication intended for the I/O subsystem component, the first data receiving means receives the data and when the I/O subsystem component receives a second data return communication intended for the I/O subsystem component, the second data receiving means receives the data.

12. The interface apparatus set forth in claim 10 wherein:

the I/O communications further include a system component message communication having a type and specifying an operation in which a message is transferred from the I/O subsystem component to a non-memory system component;

the third plurality of lines further carries a control word during a first I/O subsystem bus cycle and a message during a second I/O subsystem bus cycle of the system component message communication, the control word identifying the type of system component message communication and identifying the system component to which the message is to be transferred; and

the second output means further outputs the control word during the first I/O subsystem bus cycle of the system component message communication.

13. The interface apparatus set forth in claim 10 wherein:

the system components are connected by a system bus which carries system communications including system component message communications and includes a busy line for carrying a busy signal which indicates to a system component which was the source of a system component message communication that the system component message communication cannot presently be sent;

the I/O subsystem bus further includes a system component message not ready line and is coupled to the system bus by means of a system bus interface which converts a system component message communication destined for the I/O subsystem component to a corresponding I/O subsystem message communication and an I/O subsystem message communication destined for a system component to a corresponding system component message communication; and

the interface apparatus further includes system component message not ready signal output means connected to the system component message not ready line for outputting a system component message not ready signal when the I/O subsystem component cannot respond to a system component message communication destined for the I/O subsystem component, the system bus interface means responding to the system component message not ready signal and to a system component message communication destined for the I/O subsystem component by not converting the system component message communication to the corresponding I/O subsystem message communication and setting the busy line to indicate that the I/O subsystem system component is busy,

whereby the system bus immediately becomes available for any system communication other than a system component message communication destined for the I/O subsystem component.

14. The interface apparatus set forth in claim 13 wherein:

the I/O subsystem system component includes a plurality of I/O subsystem components coupled to the I/O subsystem bus;

an I/O subsystem component of the plurality is further a source of certain I/O subsystem message communications in that the interface means places an I/O command on the first plurality of lines, a target identification for another I/O subsystem component on the second plurality of lines, and a message on the third plurality of lines during a single I/O subsystem bus cycle; and

the interface apparatus of an I/O subsystem component of the plurality which is not currently a source of an I/O subsystem message communication remains responsive to an I/O subsystem message communication whose source is not a system component while the system component message not ready line is carrying the system component message not ready signal.

15. An I/O subsystem component interface for interfacing an I/O subsystem component to an I/O subsystem bus in an I/O subsystem system component of a digital data processing system, the I/O subsystem system component including at least one I/O subsystem component and the I/O subsystem bus carrying I/O communications, which require one or more I/O subsystem bus cycles, and which include a first type of the I/O communications which the interfaced I/O subsystem component originates and provides to the I/O subsystem bus but to which the interfaced I/O subsystem component does not respond and a second type of the I/O communications which includes I/O communications originated and provided by the interfaced I/O subsystem component and to which the interfaced I/O subsystem component responds, the I/O communications being carried on the I/O subsystem bus by means of a first plurality of lines for carrying an I/O command specifying one of the I/O communications, a second plurality of lines for carrying a target identification identifying one of the I/O subsystem components, and a third plurality of lines for carrying other information required for the specified I/O communication, the I/O subsystem component interface comprising:

means for interfacing with the I/O subsystem bus when the interfaced I/O subsystem component is providing one of the first type of I/O communications including

means coupled to the first plurality of lines for providing the I/O command specifying the one I/O communication to the first plurality of lines during all of the I/O subsystem bus cycles required for the one I/O communication,

means coupled to the second plurality of lines for providing the target identification required for the one I/O communication during all of the required I/O subsystem bus cycles,

first other communication information providing means coupled to the third plurality of lines for providing a first portion of the other information required for the one I/O communication to the third plurality of lines during the first I/O subsystem bus cycle required for the one I/O communication, and

additional other communication information providing means coupled to the third plurality of lines for providing an additional portion of the other information during any remaining I/O subsystem bus cycles required for the one I/O communication; and

means for interfacing with the I/O subsystem bus when the interfaced I/O subsystem component is responding to one of the second type of I/O communications including

detection means coupled to the second plurality of lines for detecting a target identification identifying the interfaced I/O subsystem component during transfer of the one of the second type of I/O communications,

I/O command decoding means coupled to the first plurality of lines for decoding an I/O command received on the first plurality of lines during transfer of the one of the second type of I/O communications, and

other information receiving means coupled to the third plurality of lines for receiving the other I/O information on the third plurality of lines during transfer of the one of the second type of I/O communications.

16. The I/O subsystem component interface as set forth in claim 15 and wherein:

the second type of I/O communications includes a first I/O communication specifying an operation in which the interfaced I/O subsystem component receives a message included in the first I/O communication for controlling the interfaced I/O subsystem component and a second I/O communication in which the interfaced I/O subsystem component receives data included in the second I/O communication; and

the other information receiving means includes

message receiving means for receiving the message when a decoded I/O command indicates the first I/O communication and

data receiving means for receiving the data when the decoded I/O command indicates the second I/O communication.

17. The I/O subsystem component interface as set forth in claim 15 and wherein:

the other information receiving means includes first data receiving means for receiving a word of data and second data receiving means for receiving a word of data;

the second type of I/O communications include a first data return communication specifying an operation which provides a word of data which is included in the first data return communication to the first data receiving means and a second data return communication specifying an operation which provides a word of data which is included in the second data return communication to the second data receiving means; and

the first data receiving means responds to the I/O command decoding means to receive the data word when a decoded I/O command indicates the first data return communication and the second data receiving means responds to the I/O command decoding means to receive the data word when the decoded I/O command indicates the second data return communication.

18. The I/O subsystem component interface as set forth in claim 15 and wherein:

the first type of I/O communications include a first I/O communication which requires two I/O subsystem bus cycles and which transfers a first data word and a second I/O communication which requires three I/O subsystem bus cycles and which transfers a first data word and a second data word;

the additional other communication information providing means includes a first data output means which outputs the first data word for both first and second I/O communications and a second data output means which outputs the second data word for the second I/O communication; and

the first data output means outputs the first data word for both first and second I/O communications to the third plurality of lines during the second I/O subsystem bus cycle and the second data output outputs the second data word for the second I/O communication to the third plurality of lines during the third I/O subsystem bus cycle.

19. An I/O subsystem component used in an I/O subsystem for coupling a peripheral device to a synchronous I/O subsystem bus, the I/O subsystem including at least one I/O subsystem component and being a system component of a digital data processing system which includes other system components (at least one of which is a memory means) which are coupled indirectly to the I/O subsystem bus and the I/O subsystem bus carrying a plurality of I/O communications which require one or more I/O subsystem bus cycles and including a first plurality of lines for carrying an I/O command specifying one of the I/O communications during all of the I/O subsystem bus cycles required for the specified communication, a second plurality of lines for carrying a target identification identifying an I/O subsystem component involved in the specified communication during all of the I/O subsystem bus cycles required for the specified communication, and a third plurality of lines for carrying information including messages and data as required for the specified communication, the I/O subsystem component comprising:

interface means for coupling to the I/O subsystem bus for providing an I/O communication by providing an I/O command to the first plurality of lines during all I/O subsystem bus cycles required for the I/O communication, providing a target identification to the second plurality of lines during all I/O subsystem bus cycles required for the I/O communication, and providing the information to the third plurality of lines, the information varying from I/O subsystem bus cycle to I/O subsystem bus cycle as required for the I/O communication, and responding to an I/O communication by receiving an I/O command from the first plurality of lines, receiving a target identification from the second plurality of lines, and if the I/O command and the target identification indicates an I/O communication destined for the I/O subsystem component, receiving the information from the third plurality of lines;

device adapter means coupled between the peripheral device and the interface means for providing data to and receiving data from the peripheral device; and

control means to the interface means and the device adapter means and responsive to the interface means and to the device adapter means for controlling the I/O subsystem component to originate and respond to the I/O communications,

and wherein the I/O communications include

and I/O memory write communication which requires at least two I/O subsystem bus cycles and which specifies an operation in which data include in the I/O memory write communication is transferred between the I/O subsystem component and a location in the memory means specified by a memory address included in the I/O memory write communication, the I/O memory write communication being provided in that the control means provides the I/O command specifying the I/O memory write communication, the target identification of the I/O subsystem component, and a memory address to the interface means, the interface means providing the memory address on the third plurality of lines during the first I/O subsystem bus cycle and the data during any remaining I/O subsystem bus cycles,

an I/O subsystem message communication which requires a single I/O subsystem bus cycle and specifies an operation in which a message is transferred to a second I/O subsystem component, the I/O subsystem message communication being provided by the I/O subsystem component in that the control means provides the I/O command for the I/O subsystem message communication, the target identification for the second I/O subsystem component, and the message to the interface means and the interface means places the I/O command on the first plurality of lines, the target identification on the second plurality of lines, and the message on the third plurality of lines for the single I/O subsystem bus cycle, and the I/O subsystem message communication being responded to by the second I/O subsystem component in that an interface means of the second I/O subsystem component receives the message on the third plurality of lines and a control means of the second I/O subsystem component interprets the received message and controls the second I/O subsystem component in accordance therewith, and an I/O subsystem data return communication which requires a single I/O subsystem bus cycle and specifies an operation in which data is provided to the I/O subsystem component, the I/O subsystem responding to the I/O subsystem data return communication in that the interface means receives the data on the third plurality of lines.

20. The I/O subsystem component as set forth in claim 19 and wherein the interface means comprises:

first output means coupled to the first plurality of lines and to the control means for receiving the I/O command from the control means and outputting the I/O command to the first plurality of lines;

second output coupled to the second plurality of lines and to the control means for receiving the target identification from the control means and outputting the target identification to the second plurality of lines;

third output means coupled to the control means and to the third plurality of lines for receiving the memory address from the control means and outputting the memory address to the third plurality of lines during the first I/O subsystem bus cycle of the memory write communication;

fourth output means coupled to the control means and the device adapter means and to the third plurality of lines for receiving the data from the device adapter means and the control means and outputting the data to the third plurality of lines during the second I/O subsystem bus cycle of the I/O memory write communication;

target identification receiving means coupled to the second plurality of lines for receiving the target identification and determining whether the received target identification matches an identification of the I/O subsystem component;

I/O command receiving and decoding means coupled to the first plurality of lines for responding to a match detected by the target identification receiving means by receiving and decoding the I/O command on the first plurality of lines;

message receiving means coupled to the third plurality of lines and to the control means and responsive to the I/O command decoding means for receiving the message on the third plurality of lines when the target identification and the I/O command indicate that the I/O communication is an I/O subsystem message communication to which the I/O subsystem component is to respond and providing the message to the control means; and

data receiving means coupled to the third plurality of lines, to the control means, and to the device adapter means and responsive to the I/O command decoding means for receiving data on the third plurality of lines when the target identification and the I/O command indicate that the I/O communication is an I/O subsystem data return communication to which the I/O subsystem component is to respond.

21. The I/O subsystem component as set forth in claim 19 and wherein:

the control means includes means for specifying a direct memory access operation; and

when the direct memory access operation has been specified and the I/O subsystem component is transferring the I/O memory write communication, the device adapter means provides the data to the interface means and when the direct memory access operation has been specified and the I/O subsystem component is responding to the I/O subsystem data return communication, the device adapter means takes the data from the interface means.

22. The I/O subsystem component as set forth in claim 21 and wherein:

the interface means includes memory address incrementing means and

when the direct memory access operation has been specified, the control means provides a start address for a first one of a sequence of I/O memory write communications and the device adapter means employs the address incrementing means to provide memory addresses for the remaining I/O memory write communications in the sequence.

23. The I/O subsystem component set forth in claim 19 wherein:

the I/O communications further include a system component message communication which requires at least two I/O subsystem bus cycles and which specifies an operation in which a message is transferred between the I/O subsystem component and a non-memory system component, the system component message communication being provided by the I/O subsystem component in that the control means provides the I/O command for the system component message communication, the target identification for the I/O subsystem component, a control word identifying a type of system component message communication and the system component that is the destination of the system component message communication, and a message to the interface means, and the interface means provides the control word during the first I/O subsystem bus cycle and the message for any remaining I/O subsystem bus cycles.

24. The I/O subsystem component as set forth in claim 23 and wherein the interface means comprises:

first output means coupled to the first plurality of lines and to the control means for receiving the I/O command from the control means and outputting the I/O command to the first plurality of lines;

second output means coupled to the second plurality of lines and to the control means for receiving the target identification from the control means and outputting the target identification to the second plurality of lines;

third output means coupled to the control means and to the third plurality of lines for receiving the memory address from the control means and outputting the memory address to the third plurality of lines during the first I/O subsystem bus cycle of the memory write communication, for receiving the control word from the control means and outputting the control word to the third plurality of lines during the first I/O subsystem bus cycle of the system component message communication, and receiving a message from the control means and outputting the message to the third plurality of lines during the single I/O subsystem bus cycle of the I/O subsystem message communication;

fourth output means coupled to the control means and the device adapter means and to the third plurality of lines for outputting the data to the third plurality of lines during the second I/O subsystem bus cycle of the I/O memory write communication;

target identification receiving means coupled to the second plurality of lines for receiving the target identification and determining whether the received target identification matches an identification of the I/O subsystem component;

I/O command receiving and decoding means coupled to the first plurality of lines for responding to a match detected by the target identification receiving means by receiving and decoding the I/O command on the first plurality of lines;

message receiving means coupled to the third plurality of lines and to the control means and responsive to the I/O command decoding means for receiving the message on the third plurality of lines when the target identification and the I/O command indicate that the I/O communication is an I/O subsystem message communication to which the I/O subsystem component is to respond and providing the message to the control means; and

data receiving means coupled to the third plurality of lines, to the control means, and to the device adapter means and responsive to the I/O command decoding means for receiving data on the third plurality of lines when the target identification and the I/O command indicate that the I/O communication is an I/O subsystem data return communication to which the I/O subsystem component is to respond.