Peripheral device controller with an EEPROM with microinstructions for a RAM control store

• US 5,101,490 A
• Filed: 01/10/1989
• Issued: 03/31/1992
• Est. Priority Date: 01/10/1989
• Status: Expired due to Term

• Current Assignee: Honeywell Bull Incorporated
• Original Assignee: Bull HN Information Systems Incorporated (Atos SE)
• Inventors: Gardner, Joseph P., Bradley, John W., Votolato, Alfred F., Getson, Edward F. Jr.
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Geckil, Mehmet
• Application Number:
  US07/295,318
• Time in Patent Office: 1,176 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/15
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405
• CPC Class Codes: G06F 3/0601 Interfaces specially adapted for storage systems
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 9/4411 Configuring for operating with peripheral devices; Loading of device drivers

Abstract

A peripheral device controller has an EEPROM which stores microinstructions to be placed in a random access memory control store. The EEPROM also stores peripheral configuration information. This information is obtained by polling the peripheral devices connected to the controller and storing the resulting information in the EEPROM. Upon powering up, the microinstructions stored in the EEPROM are transferred to the control store via execution of instructions held in a boot PROM. The controller, therefore, provides a fast control store while maintaining permanence of the microinstructions after power is extinguished. Means are also provided to update the control store and EEPROM. The EEPROM may upon CPU command be updated with new microinstructions held in main memory or obtained from peripheral devices.

Claims

1. A method, in a system comprising a Central Processing Unit having a memory for storing data including microinstructions for control of a peripheral device controller, a peripheral device controller coupled to said Central processing Unit and a plurality of peripheral devices coupled to said controller, the peripheral device controller having at least one microprocessor for directing the operations of said controller and a control store coupled to said at least one microprocessor for storing microinstructions for the at least one microprocessor, comprising the steps of:

a storing a plurality of microinstructions, for execution by the at least one microprocessor, in an EEPROM coupled to said control store;

b unloading the plurality of microinstructions, from the EEPROM into the control store;

c instructing the at least one microprocessor in the peripheral device controller to reload a new plurality of microinstructions into the EEPROM;

d using the at least one microprocessor operating on microinstructions from the control store to transfer the new plurality of microinstructions from the memory of the Central Processing Unit into the EEPROM; and

e unloading the new plurality of microinstructions from the EEPROM into the control store.

2. A method as recited in claim 1 further comprising the steps of transferring the new plurality of microinstructions to a data buffer before transferring them into the EEPROM.

3. A method as recited in claim 1 wherein the memory further comprises a system main memory.

4. A method as recited in claim 1 further comprising the step of interrogating peripheral devices by the processor in order to surmise configuration information and loading that configuration information into the EEPROM using the at least one microprocessor.

5. A method as recited in claim 1 wherein the new plurality of microinstructions are unloaded from the EEPROM into the control store using a boot PROM.

9. A peripheral device controller as recited in claim 1 further comprising a boot PROM, coupled to said processor, for storing boot microinstructions to enable the microinstructions stored in the EEPROM to be read into the control store.

6. A method of managing peripheral configuration information in a data processing system having a Central Processing Unit and a peripheral device controller which controls the data transfer operations between a plurality of peripheral devices and said CPU comprising the steps of:

a) using a microprocessor in the peripheral device controller to query peripheral devices to obtain in peripheral configuration information;

b) storing the configuration information in a data buffer coupled to said microprocessor;

c) using said microprocessor in the peripheral device controller, transferring the configuration information from the data buffer into an EEPROM, coupled to said microprocessor, as a table;

d) upon subsequent powering up of the data processing system, using the CPU to query the peripheral device controller; and

e) passing the configuration information held as a table in the EEPROM to the CPU in response to the CPU query.

7. A peripheral device controller for controlling data transfers between a data processing system bus of a central processing unit, having a memory for storing data including microinstructions for control of the peripheral device controller, and a plurality of peripheral devices comprising:

a a processor for executing microinstructions which controls data transfer between the peripheral device controller and said plurality of peripheral devices;

b a control store, coupled to said processor, comprising a random access memory for storing microinstructions that are executed by the processor;

c an electrically erasable programmable read only memory (EEPROM), coupled to said control store and said processor, for storing as contents microinstructions for execution by the processor;

d means for loading the contents of the EEPROM into the control store for subsequent execution by the processor;

e means for instructing the processor to update the contents of the EEPROM by instructing the processor to reload a new plurality of instructions into the EEPROM and, using the processor, operating on microinstructions from the control store, transferring the new plurality of microinstructions from the central processing unit into the EEPROM, and unloading the new plurality of microinstructions from the EEPROM into the control store.

8. A peripheral device controller as recited in claim 7 wherein the processor in the controller interrogates said plurality of peripheral devices to obtain information on a configuration of said plurality of peripheral devices and said configuration information is stored in the EEPROM.

10. A peripheral device controller as recited in claim 7 wherein the processor further comprises a plurality of microprocessors.

11. A peripheral device controller for controlling data transfer between a data processing system bus of a Central Processing Unit (CPU) and a plurality of peripheral devices comprising

a at least one microprocessor for executing microinstructions to control data transfers between the controller and said plurality of peripheral devices and to interrogate the peripheral devices to obtain information of a configuration of said peripheral devices;

b a buffer for storing the configuration information from the peripheral devices;

c a control store, coupled to said microprocessor, comprising a random access memory for storing the microinstructions that are executed by the at least one microprocessor;

d an EEPROM, coupled to said control store and said microprocessor, for storing the microinstructions and peripheral configuration information of said plurality of peripheral devices, the peripheral configuration information being transferred to the EEPROM from the data buffer by the microprocessor;

e means coupled to said microprocessor, for storing boot microinstructions which when executed unload the microinstructions of the EEPROM into the control store for use by the at least one microprocessor;

f means for updating the EEPROM by instructing the at least one microprocessor to reload the EEPROM; and

g means for responding to a query from the CPU to pass the peripheral configuration information to the CPU.