Method of fabricating a thin film transistor

• US 5,102,813 A
• Filed: 05/30/1989
• Issued: 04/07/1992
• Est. Priority Date: 05/30/1988
• Status: Expired due to Fees

• Current Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Original Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Inventors: Nijs, Johan F. A., Baert, Kris A. E. F., Kobayashi, Kazuhiro
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Wilczewski, M.
• Application Number:
  US07/358,952
• Time in Patent Office: 1,043 Days
• Field of Search: 437/40, 437/41, 437/101, 437/225, 437/233, 437/234, 437/2, 357/23.7, 357/2, 357/4, 148/DIG. 1, 148/DIG. 122
• US Class Current: 438/151
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: Y10S 148/122 Polycrystalline

Abstract

A thin film transistor is produced by applying onto a non-silicon foundation, a thin film of silicon semiconductor material under such conditions that polycrystalline or microcrystalline material is formed. Source and/or drain regions of doped semiconductor material are then formed onto the film; following by applying insulating material onto the film, and a gate region onto the insulating material. The source and/or drain regions are applied so that such regions have a crystalline structure that depends upon the crystalline structure of the underlying thin film. The resulting source and drain regions have high lateral conductivity so that source and drain contacts can be made with reduced cross-sectional areas. The method may employ a self-alignment process to simplify device production.

Claims

1. A method of producing a thin film transistor, comprising:

applying onto a non-silicon foundation a thin film of silicon semiconductor material under such condition that polycrystalline or microcrystalline material is formed;

forming source and/or drain regions of a doped semiconductor material on said film;

applying insulating material onto said film; and

forming a gate region on said insulating material;

wherein forming said source and/or drain regions includes depositing such semiconductor material by a PECVD process in which an etching gas is present to etch oxide from the film such that said source and/or drain regions at least in the region of said thin film have a crystalline structure that depends upon the crystalline structure of said thin film and said source and drain regions have a conductivity greater than or equivalent to approximately 5 mhos per cm.

2. A method according to claim 1, further comprising the step of subjecting said film to a HF dip prior to introducing said film into a PECVD apparatus.

3. A method according to claim 2, in which said semiconductor material is deposited under conditions for depositing amorphous silicon, after which the so-formed structure is annealed for a predetermined time period.

4. A method according to claim 3, in which annealing is performed at a temperature under 700°

C.

5. A method according to claim 2, in which said semiconductor material is deposited under conditions for depositing microcrystalline material.

6. A method according to claim 5, in which the so-formed structure is annealed for a predetermined time period.

7. A method according to claim 1, in which said semiconductor material is deposited under microcrystalline conditions and said etching gas is SiH_n F_4-n (n=0,1,2,3).

8. A method according to claim 1, in which the etching gas is SiF₄.

9. A method according to claim 1, in which the so-formed structure is annealed for a predetermined time period.