Method of fabricating a composite inverse T-gate metal oxide semiconductor device

• US 5,102,815 A
• Filed: 10/29/1991
• Issued: 04/07/1992
• Est. Priority Date: 12/19/1990
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Sanchez, Julian J. B.
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US07/784,577
• Time in Patent Office: 161 Days
• Field of Search: 437/27, 437/40, 437/41, 437/44, 437/187, 437/186, 437/189, 437/192, 437/193, 437/228, 437/233, 357/23.3, 357/23.5, 156/643
• US Class Current: 438/305
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7836 with a significant overlap between the lightly doped extension and the gate electrode H01L29/7834, H01L29/7835 take precedence

Abstract

A high speed submicron metal-oxide-semiconductor transistor which exhibits a high immunity to hot electron degradation. An inverse T-gate comprising a polysilicon upper member and a tungsten lower member is formed on a p type substrate. A gate insulating layer is formed between the composite gate and the p type substrate. A pair on n- source/drain regions are formed apart in the p type substrate in alignment with the sides of the polysilicon upper member for forming a lightly doped drain region. An oxide sidewall spacer is formed adjacent to each side of the polysilicon upper member on the tungsten lower gate member for forming a mask for a n+ source/drain implant. The n+ source/drain implant is made in the n- source/drain regions in alignment with the oxide sidewall spacers for providing a source and a drain for the transistor. The tungsten lower gate member improves the transistors performance and makes the transistor viable for VLSI manufacturing techniques. The performance of the device can be further improved by placing silicide on the source gate and drain regions. The reliability of the device can be further improved by grading the doping of the drain an additional time.

Claims

1. In a process for making a metal-oxide-semiconductor transistor on a p type substrate comprising the steps of:

forming an oxide layer on said p type substrate;

forming a tungsten layer on said oxide layer;

forming a polysilicon layer on said tungsten layer;

forming an upper gate member of a first length from said polysilicon layer;

forming a first source region and a first drain region in said p type substrate in alignment with said length of said polysilicon upper gate member for forming a pair of lightly doped regions;

forming a sidewall spacer on adjacent sides of said polysilicon upper gate member on said tungsten layer for providing alignment for a second source region and a second drain region and for defining a lower gate member;

forming a second source region and a second drain region in said first source region and said first drain region, respectively, in alignment with the outer edges of said sidewall spacers; and

etching said tungsten layer over said second source region and said second drain region for forming said tungsten lower gate member.

2. The process for making a metal-oxide-semiconductor transistor of claim 1 further comprising the steps of:

forming a second sidewall spacer adjacent to each of said first sidewall spacers covering said tungsten lower gate member for preventing said second source region and said second drain region from becoming shorted to said tungsten lower gate member by a silicide layer;

forming silicide on said second source region and said second drain region and on said polysilicon upper gate member for reducing the contact resistance of the transistor.

3. In a process for making a metal-oxide-semiconductor transistor on a p type substrate comprising the steps of:

forming an oxide layer on said p type substrate;

forming a tungsten layer on said oxide layer;

forming a polysilicon layer on said tungsten layer;

forming an upper gate member of a first length from said polysilicon layer;

forming a first source region and a first drain region in said p type substrate in alignment with said first length of said polysilicon upper gate member for forming a pair of lightly doped regions;

forming a sidewall spacer on adjacent sides of said polysilicon upper gate member on said tungsten layer for providing alignment for a second source region and a second drain region and for defining a lower gate member;

forming a second source region and a second drain region in said first source region and said first drain region, respectively, in alignment with the outer edges of said sidewall spacers;

etching said tungsten layer over said second source region and said second drain region for forming said tungsten lower gate member;

forming a second sidewall spacer adjacent to each of said first sidewall spacers for providing alignment for a third source region and a third drain region; and

forming a third source region and a third drain region in said second source region and said second drain region, respectively, in alignment with said second oxide sidewall spacers.

4. The process for making a metal-oxide-semiconductor transistor of claim 3 further comprising the steps of:

forming silicide on said third source region and said third drain region and on said polysilicon upper gate member for reducing the contact resistance of the transistor.

5. In a process for making a metal-oxide-semiconductor transistor on a n type substrate comprising the steps of:

forming an oxide layer on said n type substrate;

forming a tungsten layer on said oxide layer;

forming a polysilicon layer on said tungsten layer;

forming an upper gate member of a first length from said polysilicon layer;

forming a first source region and a first drain region in said n type substrate in alignment with said length of said polysilicon upper gate member for forming a pair of lightly doped regions;

forming a sidewall spacer on adjacent sides of said polysilicon upper gate member on said tungsten layer for providing alignment for a second source region and a second drain region and for defining a lower gate member;

forming a second source region and a second drain region in said first source region and said first drain region, respectively, in alignment with the outer edges of said sidewall spacers; and

etching said tungsten layer over said second source region and said second drain region for forming said tungsten lower gate member.