Vertical DRAM cell and method

• US 5,102,817 A
• Filed: 11/26/1990
• Issued: 04/07/1992
• Est. Priority Date: 03/21/1985
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chatterjee, Pallab K., Shah, Ashwin H.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US07/618,011
• Time in Patent Office: 498 Days
• Field of Search: 437/47, 437/52, 437/65
• US Class Current: 438/242
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

DRAM cells and arrays of cell on a semiconductor substrate, together with methods of fabrication, are disclosed wherein the cells are formed in pairs or quartets by excavating a trench or two trenches through the cell elements to split an original cell into two or four cells during the fabrication. The cells include vertical field effect transistors and capacitors along the trech sidewalls with word lines and bit lines crossing over the cells.

Claims

1. A method for forming a structure suitable for fabricating at least two semiconductor devices, comprising the steps of:

(a) forming a trench to provide first and second walls in a substrate;

(b) forming elements of said at least two devices, said elements including first and second transistors, at least a portion of said first and second transistors formed along said first and second walls respectively; and

(c) etching between said first and second transistors to isolate said first and second transistors by removing material formed in said trench during said step of forming elements of said at least two devices, such that said first transistor comprises an element of one of said at least two devices and said second transistor comprises an element of another one of said at least two devices.

2. A method as in claim 1 wherein said first and second walls are substantially perpendicular to said surface.

3. A method as in claim 1, wherein said transistors include an insulating layer.

4. A method as in claim 3 wherein said insulating layer includes an oxide.

5. A method as in claim 1 wherein one of said transistors extends along said first wall to an adjacent wall.

6. A method as in claim 1 wherein step (b) includes forming a doped region in an area of at least one of said first and second walls.

7. A method as in claim 1 wherein step (b) includes forming a contact to a doped region in at least one of said first and second walls.

8. A method as i claim 1 wherein step (b) includes forming a capacitor in addition to said transistors.

9. A method as in claim 1 wherein step (b) includes forming at least one of said first and second transistors with at least a portion of the channel of said at least one transistor along at least one of said first and second walls and a capacitor along at least one of said first and second walls.

10. A method as in claim 1 including the step of after step (c) filling said trench with an insulating layer.

11. A method as in claim 10 wherein said insulating layer includes an oxide.

12. A method for forming a device comprising the steps of:

(a) forming a trench in a substrate to provide first and second walls in said substrate;

(b) forming first and second capacitor plates separated from said first and second walls, respectively, by a dielectric material; and

(c) forming first and second transistors said first transistor controlling current flowing substantially parallel to said first wall and said second transistor controlling current flowing substantially parallel to said second wall.

13. A method as in claim 12 where said first transistor includes a channel formed in semiconductive material separated from said first wall by a dielectric.

14. A method as in claim 13 where said first transistor includes a gate formed in said first wall.

15. A method as in claim 12 where said second transistor includes a channel formed in semiconductive material separated from said second wall by a dielectric.

16. A method as in claim 15 where said second transistor includes a gate formed in said second wall.

17. A method as in claim 12 further including the step of forming a heavily doped region in said first wall adjacent to said first capacitor plate.

18. A method as in claim 12 further including the step of forming a heavily doped region in said second wall adjacent to said second capacitor plate.

19. A method as in claim 12 further including the step of forming heavily doped regions in said first and second walls adjacent to said first and second capacitor plates, respectively, and forming a conductive region electrically connecting said heavily doped regions.

20. A method as in claim 19 wherein said conductive region is formed in said substrate.

21. A method as in claim 20 wherein said conductive region is formed by doping a portion of said substrate.

22. A method for forming a device comprising the steps of:

(a) forming a first insulating layer on the surface of a substrate;

(b) forming a conductor on the surface of said insulating layer;

(c) forming a trench through said conductor, said insulating layer and into said substrate, said trench splitting said conductor into first and second conductors;

(d) forming a second insulating layer on the surface of said trench;

(e) forming a first semiconductive layer on the surface of said second insulating layer, said first semiconductive layer being separated from said first conductor and a first wall of said substrate by said second insulating layer; and

(f) forming a second semiconductive layer on the surface of said second insulating layer, said second semiconductive layer being separated from said second conductor and a second wall of said substrate by said second insulating layer.

23. A method as in claim 22 wherein said first insulating layer is a layer of silicon dioxide.

24. A method as in claim 22 wherein said conductor comprises polycrystalline silicon.

25. A method as in claim 22 wherein said second insulating layer comprises silicon dioxide.

26. A method as in claim 22 wherein said second insulating layer comprises silicon dioxide and silicon nitride.

27. A method as in claim 22 wherein said second insulating layer is formed by thermal oxidation.

28. A method as in claim 22 wherein said first semiconductive layer comprises polycrystalline silicon.

29. A method as in claim 22 wherein said second semiconductive layer comprises polycrystalline silicon.

30. A method as in claim 22 wherein said first and second semiconductive layers are formed using the steps of:

(a) depositing a semiconductive layer on the surfaces of said trench; and

(b) anisotropically etching said semiconductive layer until the portion of said semiconductive layer on the bottom of said trench is removed, thus separating said semiconductive layer into said first and second semiconductive layers.

31. A method for forming a device comprising the steps of:

(a) forming a trench in a substrate to define first and second walls;

(b) forming a first insulating layer on said first and second walls;

(c) forming a first conductive layer on said first insulating layer adjacent said first and second walls;

(d) removing a portion of said first conductive layer adjacent said first and second walls;

(e) removing the portion of said insulating layer exposed by the removal of a portion of said first conductive layer in step (d);

(f) removing a portion of said insulating layer between said first conductive layer and said first and second walls, thus forming first and second crevices;

(g) filling said first and second crevices with a conductive material;

(h) forming first and second source regions in electrical contact with said conductive material;

(i) forming a second insulating layer on said exposed portions of said first and second walls, said conductive material and said first layer of conductive material;

(j) forming a second conductive layer on said second insulating layer; and

(k) forming first and second drain regions in said first and second walls adjacent to said second insulating layer and spaced from said first and second source regions.

32. A method as in claim 31 wherein said first and second walls are perpendicular to a major face of said substrate.

33. A method as in claim 31 wherein said trench has a rectangle shape.

34. A method as in claim 31 wherein said first conductive layer includes dopant atoms and said first and second source regions are formed by diffusing said dopant atoms through said conductive material into said first and second walls.

35. A method as in claim 31 further comprising the step of etching between said first and second walls subsequent to step k to remove material formed in said trench, thereby dividing said first conductive layer into first and second capacitor plates and dividing said second conductive layer into first and second gates.

36. A method as in claim 35 wherein said step of etching separates said first drain region, said first source region said first gate region, said first capacitor plate from said second drain, said second gate, said second source and said second capacitor plate.

37. A method as in claim 35 further including the step of filling the trench produced by said etching step with an insulating material.