Semiconductor integrated circuit chip having an identification circuit therein

• US 5,103,166 A
• Filed: 09/06/1990
• Issued: 04/07/1992
• Est. Priority Date: 05/23/1990
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Seok, Yong-sik, Jeon, Dong-su
• Primary Examiner(s): Wieder, Kenneth A.
• Assistant Examiner(s): BURNS, WILLIAM
• Application Number:
  US07/578,284
• Time in Patent Office: 579 Days
• Field of Search: 324/158 R, 324/158 P, 324/158 D, 324/158 T, 324/537, 324/73.1, 307/303, 307/304, 437/8, 437/7
• US Class Current: 324/750.15
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: H01L 2223/5444 for electrical read out
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 27/0203 Particular design considerations for integrated circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor integrated circuit chip has an identification circuit connected between a power voltage supply terminal and one of the input terminals of the chip. The identification circuity includes a voltage limiter to limit the input potential difference between the power voltage supply terminal and the input terminal to a predetermined voltage level. The identification circuit further includes an option device connected to the voltage limiter to provide identification information of the chip. According to the identification circuit, chip identification testing may be achieved with existing input/output and power supply terminals, thereby eliminating the need for extra test and diagnosis pins or additional identification equipment employed during testing.

Claims

1. In a semiconductor integrated circuit chip having a pair of power supply terminals, a plurality of input terminals and an identification circuit means connected between one of said power supply terminals and one of said input terminals, the improvement wherein said identification circuit means comprises:

a voltage limiter for limiting the input potential difference between said one power supply terminal and said one input terminal to a predetermined limiting voltage level; and

option means connected in series to said voltage limiter for providing identification information indicative of said chip.

2. A semiconductor integrated chip as defined in claim 1, wherein said voltage limiter comprises a plurality of serially connected MOS transistors, each of said MOS transistors having a gate connected to a drain thereof, whereby said predetermined limiting voltage level is set to be a sum of the threshold voltages of said MOS transistors.

3. A semiconductor integrated circuit chip as defined in claim 1, wherein said option means comprises a fuse which is optionally one of connected or disconnected.

4. A semiconductor integrated circuit chip as defined in claim 1, wherein said option means comprises a MOS transistor having a gate and a source which are optionally one of connected or disconnected by a metal wire.

5. A semiconductor integrated circuit as defined in claim 1, wherein said option means comprises a plurality of identification paths connected in parallel, each said identification path having a MOS transistor connected in series to a fuse, said MOS transistor having a gate connected to a drain thereof, and said identification information being set according to said fuses being optionally one of connected or disconnected.

6. In a semiconductor integrated circuit chip having a pair of power supply terminals, at least three input terminals and an identification circuit means connected with one of said power supply terminals and with said three input terminals, the improvement wherein said identification circuit means comprises:

voltage limiting means for limiting the potential difference between said one power supply terminal and one of said three input terminals to a predetermined limiting voltage level and for generating a predetermined control voltage by dividing the limiting voltage level;

option means connected between the remaining two of said three input terminals for providing identification information indicative of said chip; and

switch means connected in series to said option means, said switch means being controlled by said control voltage supplied from said voltage limiting means.

7. A semiconductor integrated circuits chip as defined in claim 6, wherein said voltage limiting means comprises:

a plurality of serially connected MOS transistors, each of which has a gate connected to a respective drain thereof; and

a resistor connected to said plurality of MOS transistors, whereby said limiting voltage level is a sum of a terminal voltage of said resistor and the threshold voltages of said MOS transistors, and said control voltage is said terminal voltage of said resistor.

8. A semiconductor integrated circuits chip as defined in claim 6, wherein said option means comprises a plurality of fuses and said switch means comprises a plurality of MOS transistors, each of said plurality of fuses being serially connected to a corresponding one of said plurality of said MOS transistors, said MOS transistors having gates coupled to receive said control voltage, and said identification information of said chip being determined according to whether said fuses are one of connected or disconnected.

9. An integrated circuit chip comprising:

internal circuit means;

a pair of power supply terminals for supplying power to said internal circuit means;

a plurality of input terminals for supplying signals to said internal circuit means; and

identification circuit means, coupled between one of said power supply terminals and one of said input terminals, comprising;

voltage limiting means for limiting a potential difference between said one power supply terminal and said one input terminal to a predetermined voltage level; and

option means coupled to said voltage limiting means for optionally permitting current to flow therethrough;

whereby said chip is identified according to whether said current flows through said identification circuit means.

10. An integrated circuit chip comprising:

internal circuit means;

a pair of power supply terminals for supplying power to said internal circuit means;

at least three input terminals for supplying signals to said internal circuit means; and

identification circuit means, coupled to one of said power supply terminals and at least three of said input terminals, comprising;

voltage limiting means, coupled between said one power supply terminal and a first of said three input terminals, for limiting a potential difference between said one power supply terminal and said first input terminal to a predetermined voltage level and for generating a control voltage, said voltage limiting means comprising a plurality of MOS transistors connected in series with a resistor;

a plurality of identification current paths coupled in parallel between a second and a third of said input terminals, each said path comprising a MOS transistor connected in series with a disconnectable member, said MOS transistor having a gate coupled to receive said control voltage generated by said voltage limiting means;

whereby said chip is identifiable according to a sum of currents flowing through said plurality of identification current paths.

11. An integrated circuit chip according to claim 10, wherein said disconnectable member comprises a fuse which may be optionally connected or disconnected.

12. An integrated circuit chip according to claim 10, wherein said disconnectable member comprises a metal wire disposed between a gate and a source of a MOS transistor, said gate and source being optionally connected or disconnected by said metal wire.