Sigma-delta modulator

• US 5,103,228 A
• Filed: 06/10/1991
• Issued: 04/07/1992
• Est. Priority Date: 06/22/1990
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Hart, Cornelis M., Voorman, Johannes O.
• Primary Examiner(s): Pellinen, A. D.
• Assistant Examiner(s): Young, Brian K.
• Application Number:
  US07/713,181
• Time in Patent Office: 302 Days
• Field of Search: 341/143, 341/126, 341/155, 375/25, 375/26, 375/27, 375/28, 375/29, 375/33, 375/34
• US Class Current: 341/143
• CPC Class Codes: H03M 3/43 the quantiser being a single bit one
• CPC Class Codes: H03M 3/438 the modulator having a higher order loop filter in the feedforward path
• CPC Class Codes: H04N 19/00 Methods or arrangements for coding, decoding, compressing or decompressing digital video signals

Abstract

1-Bit signma-delta modulator having a loop filter (5,6,8), a first negative feedback loop (13,7,8) and a second negative feedback loop (14,4,5,6,8). The filter sections 5 and 8 are passive filter elements and filter section 6 is a high-gain active filter element. A circuit of this type makes a very high clock rate possible in the decision switch 10.

Claims

1. Sigma-delta modulator for converting an input signal into a 1-bit digital output signal, comprising:

a low-pass filter including a series connection of first, second and third sections having at least first order filter functions, each section having an input and having an output for producing respective first, second and third section signals;

quantization means for converting the third section signal into the 1-bit digital output signal and for producing first and second feedback signals in response to the digital output signal;

a first subtractor stage for producing a first difference signal from the second section signal and the first feedback signal and for applying the first difference signal to the input of the third filter section;

a second subtractor stage for producing a second difference signal form the input signal and the second feedback signal and for applying the second difference signal to the input of the first filter section; and

coupling means for coupling the first section signal to the input of the second filter section,

characterized in that the first and third filter sections as regards the signal frequencies are arranged as passive networks, and in that the second filter section is arranged as an active filter stage.

2. Sigma-delta modulator as claimed in claim 1, characterized in that the quantization means comprise:

a first latch for measuring the third section signal during a first phase of a clock signal and for producing a first latched signal during a second phase of the clock signal; and

a second latch for measuring the first latched signal during the first phase of the clock signal and for producing a second latched signal during the second phase of the clock signal, the first and second latched signals functioning as the first and second feedback signals, respectively.

3. Sigma-delta modulator as claimed in claim 2, characerized in that the modulator further includes at least one mixer stage for replacing, during an first phase of the clock signal, the instantaneous value of one of the first and second latched signals with a fixed signal value that is independent of said instantaneous value.

4. Sigma-delta modulator as claimed in claim 3, characterized in that the mixer stage comprises

first to sixth transistors each comprising a first and a second main electrode and a control electrode;

first and second input terminals for receiving the latched signal and a signal complementary thereto, respectively;

a third input terminal for receiving the clock signal;

a first and second output terminal for delivering the feedback signal and a feedback signal complementary thereto;

first and second current sources; and

coupling means for coupling;

the control electrodes of the first and second transistors to the first input terminal;

the control electrodes of the third and fourth transistors to the second input terminal;

the first main electrodes of the first, fourth and fifth transistors to the first current source;

the first main electrodes of the second, third and sixth transistors to the second current source;

the second main electrodes of the third, fourth and sixth transistors to the second output terminal; and

the second main electrodes of the third, fourth and sixth transistors to the second output terminal; and

the control electrodes of the fifth and sixth transistors to the third input terminal.