Data processing module and video processing system incorporating same

• US 5,103,311 A
• Filed: 10/01/1990
• Issued: 04/07/1992
• Est. Priority Date: 01/11/1988
• Status: Expired due to Term

• Current Assignee: IPG Electronics 503 Limited (Coller IP Capital Limited)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Sluijter, Robert J., Huizer, Cornelis M., Dijkstra, Hendrik, Slavenburg, Gerrit A.
• Primary Examiner(s): Britton, Howard W.
• Assistant Examiner(s): Harvey, David E.
• Application Number:
  US07/593,366
• Time in Patent Office: 554 Days
• Field of Search: 358/160, 358/167, 358/22, 358/183, 382/27, 382/41, 382/42, 382/49, 364/133, 364/134, 364/131, 364/518, 364/521
• US Class Current: 348/571
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

The invention describes a processor system suitable for processing video signal samples on a real-time basis. Signals are derived from the samples for driving an imaging unit. For this purpose, one or more processor modules are provided with processor elements, operating in parallel in time, which are connected to a crossbar switch. A module contains at least one arithmetic/logic processor element and at least one memory processor element. Moreover, there is a clock device, the frequency of which bears a fixed relationship to the frequency with which the video signal samples are obtained.

Claims

1. A processor system suitable for processing video signal samples derived at a sampling frequency on a real-time basis, comprising at least one processor unit for deriving from said video signal samples, signals which are suitable for driving an imaging unit, said processor unit comprising:

at least one processor module comprising a plurality of processor elements disposed to function in parallel with one another, said processor elements including at least one processor element chosen from a group consisting of at least one arithmetic processor element, at least one logic processor element and at least one memory processor element; and

a cross bar switch to which input signals for a first processor module and output signal from processor elements belonging to additional processor modules are supplied and from which input signals for said processor elements belonging to said additional processor modules and output signals from said first processor module are obtained;

the processor system further comprising a clock device for controlling said processor unit, said clock device operating at a frequency which has a fixed relationship to said sampling frequency.

3. A video processor system according to claim 1, there are provided at least two processor units which comprise switching means enabling their connection in a series, a parallel and/or a fed-back configuration.

4. A processor system according to claim 1, further comprising at least one field memory coupled to said processor unit.

5. A processor system according to claim 1, wherein said processor unit is comprises three mutually connected processor modules.

6. A processor system according to claim 1, wherein said processor unit is constructed as a separate integrated circuit.

7. A processor system according to claim 1 comprising a plurality of processing units each comprising a multiplex/demultiplex circuit, wherein to connect between processor modules of respective processor units, each processor module is connected to a multiplex/demultiplex circuit belonging to another processor unit, and wherein a data path width between respective processor units comprises a smaller number of bits than said input and output signals of the processor modules.

8. A processor system according to claim 1, wherein each processor module is provided with three processing elements which can include arithmetic or logic processor elements, two memory processor elements and a gate processor element.

9. A processor system according to claim 8, wherein each processor element is connected to a corresponding input circuit and in that said input circuits together form the crossbar switch.

10. A processor system according to claim 8 wherein the arithmetic and logic processor element (MILL) each comprise an arithmetic and logic element (ALE) respectively and a control element (CTRM).

11. A processor system according to claim 8 wherein the memory processor elements comprise a memory element (ME) and a control element (CTRS).

12. A processor system according to claim 8 wherein the gate processor element is formed by a data buffer and a control element (CTRG).

13. A processor system according to claim 10 wherein each of the control elements contains a program memory.

14. A processor system according to claim 13, wherein said the program memories are constructed as RAM memories and in that each processor unit is provided with an initiation bus via which the program memories are loaded.

15. A processor system according to claim 13, wherein said program memories are constructed as ROM memories into which the respective control programs have been permanently introduced.

16. A processor system according to claim 14, wherein the initiation bus is a bit-serial bus and each control element comprises an initiation circuit.

17. A processor system according to claim 11 wherein the memory element (ME) is provided with a data memory and the respective memory processor element comprises means for transferring signals derived in parallel form from the initiation circuit in said memory processor element to the data memory.

18. A processor system according to claim 10 and wherein the arithmetic, logic elements (ALE), and memory elements (ME) are provided with silo registers which form the connection to the corresponding outputs of the crossbar switch.

19. A processor system according to claim 12, wherein the data buffer is formed in the gate processor element by equally as many silo registers as there are input/output channels.

20. A processor system according to claim 18 wherein the silo registers are written to according to a fixed sequence, while reading-out takes place in a sequence determined by the program in the program memory of the respective processor element.

21. A processor system according to claim 20, wherein the silo registers comprise a subtraction circuit in which an absolute read-out address for the respective silo register is obtained by subtracting a relative read-out address RAD supplied by the program memory from a write address.

22. A processor system according to claim 13, wherein each program memory provides capacity for a fixed cycle of branch-free instructions.

23. A processor system according to claim 22, wherein the cycle comprises a maximum of sixteen instructions.

24. A processor system according to claim 1, wherein each of the video processor units comprises a clock circuit which generates a 27 MHz clock signal for the processor modules under the control of said clock device.

25. A processor system according to claim 7 wherein the multiplex/demultiplex circuits are controlled by a 54 MHz clock signal derived from the clock device.

26. A processor system according to claim 1, wherein the frequency of the clock device bears a fixed relationship to a frequency at which consecutive video lines occur in the processor system.

27. A processor system according to claim 1, wherein said processor unit contains a reset signal conductor which is common for all the processor elements.

28. A processor system according to claim 11, wherein the capacity of the memory elements (ME) of the memory processor elements in a processor module is sufficient, when combined, to store the data relating to a video line.

29. An integrated circuit provided with a processor unit as claimed in claim 1.

30. An imaging system provided with means for receiving frame-sequential and line-sequential image information from a source device, a processor system according to claim 1 and means for effecting the imaging of an image.

31. An image storage system provided with means for receiving frame-sequential and line-sequential image information from a source device, a processor system according to claim 1 and means for effecting the image storage.

2. A processor module comprising a plurality of processor elements disposed to function in parallel with one another and a crossbar switch having a plurality of switch outputs, to which inputs as well as outputs from respective processor elements are coupled, and from which input signals for said processor elements and output signals from said processor module are obtained and further comprising buffer elements coupled to each of said switch outputs.