Event qualified testing protocols for integrated circuits

• US 5,103,450 A
• Filed: 03/12/1991
• Issued: 04/07/1992
• Est. Priority Date: 02/08/1989
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Whetsel, Lee D.
• Primary Examiner(s): ATKINSON, CHARLES
• Application Number:
  US07/668,715
• Time in Patent Office: 392 Days
• Field of Search: 371/22.1, 371/22.3, 371/22.4, 371/25.1
• US Class Current: 714/724
• CPC Class Codes: G01R 31/318555 Control logic
• CPC Class Codes: G01R 31/318558 Addressing or selecting of subparts of the device under test
• CPC Class Codes: G06F 11/267 Reconfiguring circuits for testing, e.g. LSSD, partitioning
• CPC Class Codes: G06F 2201/86 Event-based monitoring

Abstract

A set of event qualified test protocols for use in testing integrated circuits is disclosed. A boundary scan architecture for use in the integrated circuit (10) comprises input and output test registers (12,22) having functions controlled by an event qualifying module (EQM) (30). The EQM (30) receives a signal indicating a matching condition has been met. The EQM receives additional signals which indicate which testing protocol of the possible protocols is selected. The EQM (30) may control the input and output test registers (12,22) to perform a variety of tests on the incoming and outgoing data. During testing, the internal logic (20) may continue to operate at speed, thereby allowing the test circuitry to detect faults which would not otherwise be observable. A memory buffer (64) may be included to store a plurality of input data for test data. A set of standard protocols is disclosed which allows interoperability between EQMs on multiple IC'"'"'s in a circuit. By adhering to a standard set of standard event qualification protocols, all IC designs produced with the boundary scan architecture will be capable of operating together to perform advanced test operations of the circuit is response to a condition.

Claims

1. A method of testing integrated circuits comprising the steps of:

detecting a first signal on the integrated circuit to determine whether a test operation is desired;

detecting a second signal on the integrated circuit, when the first signal is detected, said second signal indicative of a desired protocol; and

performing a test operation on the integrated circuit using said desired test protocol.

2. The method of claim 1 and further comprising the step of detecting a third signal after completing said test using desired protocol, said third signal indicating that said test operation is complete.

3. The method of claim 1 wherein said step of detecting said second signal comprises the step of detecting third and fourth signals operable to indicate one of four protocols.

4. The method of claim 1 wherein the said step of performing the test comprises the step of repeating the test operation a predetermined number of times.

5. The method of claim 1 wherein said step of performing the test operation comprises the step of performing a test operation on a single data word.

6. The method of claim 5 wherein said step of performing the test operation further comprises the step of repeating said single data word test operation a predetermined number of times.

7. The method of claim 5 wherein said step of performing a single data word test operation comprises the step of outputting a test data word from the integrated circuit.

8. The method of claim 5 wherein said step of performing a single data word test operation comprises the step of storing a data word input to the integrated circuit.

9. The method of claim 1 wherein said step of performing the test operation comprises the step of performing a test operation on a sequence of data words during the occurrence of a third signal.

10. The method of claim 9 wherein said step of performing the test operation further comprises the step of repeating said step of performing the test operation during a third signal a predetermined number of times.

11. The method of claim 9 wherein said step of performing the test during a third signal comprises the step of outputting a sequence of test data from the integrated circuit while said third signal is present.

12. The method of claim 9 wherein said step of performing the test during a third signal comprises the step of storing a sequence of data input to the integrated circuit while said third signal is present.

13. The method of claim 9 wherein said step of performing the test during a third signal comprises the step of performing signature analysis on a sequence of data input to the integrated circuit while said third signal is present.

14. The method of claim 1 wherein said step of performing the test operation comprises the steps of performing a test operation on a sequence of data words, starting the test operation on a third signal and ending the test operation on a fourth signal.

15. The method of claim 14 wherein said step of performing the test operation further comprises the step of repeating said test operation between said third and fourth signals a predetermined number of times.

16. The method of claim 14 wherein said step of performing the test operation between third and fourth signals comprises the step of outputting a sequence of test data from the integrated circuit.

17. The method of claim 14 wherein said step of performing the test operation between third and fourth signals comprises the step of storing a sequence of data input to the integrated circuit.

18. The method of claim 14 wherein said step of performing the test operation between third and fourth signals comprises the step of performing signature analysis on a sequence of data input to the integrated circuit.

19. The method of claim 14 wherein said step of performing the test operation further comprises the step of resuming the test operation on a sequence of data words responsive to a fifth signal and stopping the test operation responsive to a sixth signal.

20. The method of claim 19 wherein said step of performing the test operation further comprises the step of repeating said test operation performed between said third and fourth signals and said fifth and sixth signals a predetermined number of times.

21. Apparatus for testing integrated circuits, comprising:

circuitry of an integrated circuit for detecting a first signal to determine whether a test operation is desired;

circuitry on the integrated circuit for producing an output upon detecting a second signal, said second signal being generated when the first signal is asserted, said second signal indicative of a desired protocol; and

circuitry on the integrated circuit coupled to the output producing circuitry, for receiving and/or transmitting data to be tested, and operable for performing a test operation using said desired protocol.

22. The apparatus of claim 21 wherein the said circuitry for performing the test comprises counting circuitry for performing the test operation a predetermined number of times.

23. The apparatus of claim 21 wherein said circuitry for performing the test operation comprises logic circuitry operable performing a test operation on a single data word.

24. The apparatus of claim 21 wherein said circuitry for performing the test operation comprises enabling circuitry for performing a test operation on a sequence of data words during the occurrence of a third signal.

25. The apparatus of claim 21 wherein circuitry for performing the test operation comprises logic circuitry for performing a test operation on a sequence of data words, starting the test operation responsive to a third signal and stopping the test operation responsive to a fourth signal.

26. The apparatus of claim 25 wherein said circuitry for performing the test operation comprises logic circuitry for resuming the test operation on a sequence of data words responsive to a fifth signal and stopping the test operation responsive to a sixth signal.

27. Apparatus for testing of a plurality of integrated circuits, comprising:

circuitry on each integrated circuit for receiving a test command signal indicating a desired test protocol;

circuitry on each integrated circuit operable to perform a test operation on each integrated circuit using said desired protocol while the integrated circuits concurrently operate together functionally; and

circuitry on each integrated circuit for inputting test command signals and outputting test results while the integrated circuits concurrently operate together functionally.

28. The apparatus of claim 27 wherein the plurality of integrated circuits comprises multiple integrated circuits within the substrate of a single integrated circuit.

29. The apparatus of claim 27 wherein the plurality of integrated circuits comprises multiple integrated circuits assembled onto the substrate of a multiple chip module.

30. The apparatus of claim 27 wherein the plurality of integrated circuits comprise multiple integrated circuits assembled onto the substrate of a printed circuit board.

31. The apparatus of claim 27 wherein said circuitry for performing the test operation further comprises programmable counting circuitry for performing said test operation a programmable number of times.

32. The apparatus of claim 27 wherein said circuitry for performing the test operation comprises control circuitry for executing said test operation during the occurrence of a predetermined condition.

33. The apparatus of claim 27 wherein said circuitry for performing the test operation comprises control circuitry for executing a single test operation responsive to a predetermined condition.

34. The apparatus of claim 27 wherein said circuitry for performing the test operation comprises control circuitry for starting said test operation responsive to a first predetermined condition and stopping the test operation responsive to a second predetermined condition.

35. The apparatus of claim 34 wherein said circuitry for performing the test operation further comprises control circuitry for resuming said test operation responsive to a third predetermined condition and stopping the test operation responsive to a fourth predetermined condition.

36. The apparatus of claim 27 wherein said circuitry for performing the test operation comprises signature analysis circuitry for compressing data into a signature.

37. The apparatus of claim 27 wherein said circuitry for performing the test operation comprises a test data memory for storing data.

38. The apparatus of claim 27 wherein said circuitry for performing the test operation comprises circuitry for testing data input to said plurality of integrated circuits.

39. The apparatus of claim 38 wherein said circuitry for testing data input to said plurality of integrated circuits further comprises circuitry operable for compressing said data input into a signature.

40. The apparatus of claim 38 wherein said circuitry for testing data input further comprises circuitry for storing said data input into a test data memory.

41. The apparatus of claim 27 wherein said circuitry for performing said test operation comprises circuitry for testing data output from said plurality of integrated circuits.

42. The apparatus of claim 41 wherein the said circuitry for testing data output further comprises circuitry operable for compressing said data output into a signature.

43. The apparatus of claim 41 wherein the said circuitry for testing data output comprises circuitry for storing said data output into a test data memory.

44. The apparatus of claim 27 wherein said circuitry for performing said test operation comprises circuitry for simultaneously testing data input to and data output from integrated circuits.

45. The apparatus of claim 44 wherein the said circuitry for simultaneously testing data input and data output further comprises circuitry for compressing said data input into a signature and for compressing data output into a signature.

46. The apparatus of claim 45 wherein said circuitry for outputting test results further comprises circuitry operable to output a test signature from said signature analysis circuitry.

47. The apparatus of claim 44 wherein said circuitry for simultaneously testing data input and data output further comprises circuitry for storing said data input and data output into a test data memory.

48. The apparatus of claim 47 wherein said circuitry for outputting test results further comprises circuitry operable to output stored test data from said test data memory.

49. The apparatus of claim 27 wherein said circuitry for performing said test operation further comprises circuitry for selectively outputting test data from the integrated circuit in place of the integrated circuits functional output data.

50. A method for testing a plurality of integrated circuits, comprising the steps of:

detecting a test command signal on one or more integrated circuits indicating a desired test protocol; and

performing a test operation on one or more integrated circuits using said desired test protocol while the integrated circuits concurrently operate together functionally.

51. The method of claim 50 wherein said step of performing the test operation further comprises the step of repeating the test operation a predetermined number of times.

52. The method of claim 50 wherein said step of performing the test operation further comprises the step of testing data input to said integrated circuits.

53. The method of claim 52 wherein said step of testing data input to said integrated circuits further comprises the step of storing said data input into a memory.

54. The method of claim 52 wherein said step of testing data input to said integrated circuits further comprises the step of compressing said data input into a signature.

55. The method of claim 52 wherein said step of performing the test operation further comprises the step of testing data output from the integrated circuits.

56. The method of claim 55 wherein said step of testing data output from the integrated circuits further comprises the step of storing said data output into a memory.

57. The method of claim 56 wherein said step of testing data output from integrated circuits further comprises the step of compressing said data output into a signature.

58. The method of claim 50 wherein said step of performing the test operation on one or more integrated circuits further comprises the step of simultaneously testing data input to and data output from said integrated circuits.

59. The method of claim 58 wherein said step of simultaneously testing data input to and output from said integrated circuits further comprises the step of storing the data input and data output into a memory.

60. The method of claim 58 wherein said step of simultaneously testing data input to and output from integrated circuits further comprises the step of compressing said data input into a signature and compressing said data output into a signature.

61. The method of claim 50 wherein said step of performing the test operation on one or more integrated circuits further comprises the step of selectively outputting test data from one or more of said integrated circuits in place of outputting functional data.

62. The method of claim 50 wherein said step of performing the test operation on one or more integrated circuits further comprises the step of executing a test operation during the occurrence of a predetermined condition.

63. The method of claim 50 wherein said step of performing the test operation on one or more integrated circuits further comprises the step of executing a single test operation in response to a predetermined condition.

64. The method of claim 50 wherein said step of performing the test operation on one or more integrated circuits further comprises the step of starting the test operation in response to a first predetermined condition and stopping the test operation in response to a second predetermined condition.

65. The method of claim 50 wherein said step of performing the test operation on one or more integrated circuits further comprises the step of resuming the test operation in response to a third predetermined condition and stopping the test operation in response to a fourth predetermined condition.

66. The method of testing integrated circuits, comprising the steps of:

detecting a test command signal indicating a desired test protocol on a first integrated circuit;

detecting a test command signal on a second integrated circuit;

concurrently performing a test operation using the desired test protocol on said first and second integrated circuits without interfering with the normal operation of said first and second integrated circuits.

67. An apparatus for testing integrated circuits, comprising:

circuitry on a first integrated circuit for detecting a signal to determine whether a test operation using a predetermined test protocol is desired;

circuitry on a second integrated circuit for detecting a signal to determine whether a test operation using the said predetermined test protocol is desired; and

circuitry on the first and second integrated circuits for receiving and/or transmitting data to be tested, and operable for performing a test operation using said desired protocol concurrently on each integrated circuit without interfering with the normal operation of the integrated circuits.

68. An apparatus for testing a plurality of integrated circuits, comprising:

circuitry on each integrated circuit for receiving at test command signal indicating a desired test protocol;

circuitry on each integrated circuit operable to perform a test operation on each integrated circuit in response to a predetermined condition using said desired protocol while the integrated circuits operate together functionally; and

circuitry on each integrated circuit operable to detect the occurrence of a predetermined condition on the integrated circuit and to output a signal in response to said detected condition to said circuitry performing the test operation, said signal effectuating said test operation of said integrated circuit using said desired protocol.

69. An apparatus for testing a plurality of integrated circuits, comprising:

circuitry on each integrated circuit for receiving a test command signal indicating a desired test protocol;

circuitry on each integrated circuit operable to perform a test operation on each integrated circuit in response to a predetermined condition using said desired protocol while the integrated circuits operate together functionally; and

circuitry on each integrated circuit operable to detect the occurrence of a predetermined condition external to the integrated circuit and to output a signal in response to said detected condition to said circuitry performing the test operation, said signal effectuating said test operation of said integrated circuit using said desired protocol.

70. An apparatus for testing a plurality of integrated circuits, comprising:

circuitry on a first integrated circuit for detecting and outputting a predetermined condition; and

circuitry on a second integrated circuit for performing a test operation on said second integrated circuit in response to receiving said predetermined condition from said first integrated circuit while said first and second integrated circuits are operating normally.

71. An apparatus for testing a plurality of integrated circuits, comprising:

circuitry on a first integrated circuit for detecting a predetermined condition and outputting a signal in response;

circuitry on a second integrated circuit for detecting a predetermined condition and outputting a signal in response;

voting circuitry operable to receive said signals output from said first and second integrated circuits, and to output a global condition signal in response both received signals being true; and

circuitry on a third integrated circuit for performing a test operation on said third integrated circuit in response to receiving said global condition signal from said voting circuitry while said first, second, and third integrated circuits are operating normally.