Making and testing an integrated circuit using high density probe points

• US 5,103,557 A
• Filed: 02/16/1990
• Issued: 04/14/1992
• Est. Priority Date: 05/16/1988
• Status: Expired due to Fees

• Current Assignee: ELM TECHNOLOGY CORPORATION
• Original Assignee: Glenn J. Leedy
• Inventors: Leedy, Glenn J.
• Primary Examiner(s): Arbes, Carl J.
• Application Number:
  US07/482,135
• Time in Patent Office: 788 Days
• Field of Search: 29/407, 29/825, 29/846, 29/832, 324/158 P, 324/73 PC, 324/158 F, 437/8
• US Class Current: 438/6
• CPC Class Codes: G01R 1/06716 Elastic
• CPC Class Codes: G01R 1/07307 with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 1/0735 arranged on a flexible frame or film
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2863 Contacting devices, e.g. sockets, burn-in boards or mounting fixtures in general G01R1/04
• CPC Class Codes: G01R 31/287 Procedures; Software aspects
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: G01R 31/318505 Test of Modular systems, e.g. Wafers, MCM's
• CPC Class Codes: G01R 31/318511 Wafer Test
• CPC Class Codes: G01R 31/31905 Interface with the device under test [DUT], e.g. arrangements between the test head and the DUT, mechanical aspects, fixture
• CPC Class Codes: G01R 31/31912 Tester/user interface
• CPC Class Codes: G03F 7/70466 Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature stitching G03F7/70475
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49764 : with testing or indicating

Abstract

Each transistor or logic unit on an integrated circuit wafer is tested prior to interconnect metallization. By means of CAD software, the transistor or logic units placement net list is revised to substitute redundant defect-free logic units for defective ones. Then the interconnect metallization is laid down and patterned under control of a CAD computer system. Each die in the wafer thus has its own interconnect scheme, although each die is functionally equivalent, and yields are much higher than with conventional testing at the completed circuit level.

The individual transistor or logic unit testing is accomplished by a specially fabricated flexible tester surface made in one embodiment of several layers of flexible silicon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points on one side of the test surface. The probe points electrically contact the contacts on the wafer under test by fluid pressure.

Claims

1. A method of fine grain testing an integrated circuit at the device level comprising the steps of:

electrically contacting each one of a plurality of devices in the integrated circuit;

applying an electrical voltage to each one of the devices for a period of at least one second; and

determining after the period if each of the devices is functional

2. The method of claim 1, further comprising the step of elevating an ambient temperature of the integrated circuit by at least 25°

C.

3. The method of claim 1, further comprising, after the step of determining, the step of interconnecting the devices.

4. A method for providing discretionary interconnections at any location in an integrated circuit comprising the steps of:

providing a plurality of discretionary metal traces each being in a conductive or in a nonconductive state in the integrated circuit, each metal trace being contacted at each of its two ends by a metal contact less than one mil by one mil in size located immediately adjacent to the metal trace; and

contacting the two contacts at the ends of one trace and applying a voltage to the two contacts so a current flows through the metal trace, thereby causing the trace to change its state into the other state.

5. The method of claim 4, further comprising the step of testing the metal traces during the fabrication of the interconnections of an integrated circuit.

6. The method of claim 4, wherein each metal contact has a width of less than about 6 microns.

7. A method of testing an integrated circuit comprising the steps of:

providing a tester having at least one thousand probe points on a first side of the tester;

electrically contacting individual devices in the integrated circuit with the probe points;

vibrating the tester so as to achieve improved electrical contact; and

electrically testing the devices by providing signals to the devices through the probe points.

8. The method of claim 7, further comprising the steps of:

providing a fluid on a second side of the tester; and

vibrating the fluid so as to vibrate the tester.

9. The method of claim 7, further comprising the steps of:

providing a piezoelectric layer on a second side of the tester; and

providing a varying electrical signal to the piezoelectric layer so as to vibrate the tester.

10. A method of testing integrated circuit logic units each including electronic devices, circuitry, and contact points formed on a semiconductor wafer, comprising the steps of:

providing a support for said wafer;

providing a flexible tester surface having a thickness of no greater than 15 microns of inorganic material and having a number of probe points corresponding to said contact points of said wafer;

electrically interconnecting said probe points of said flexible tester surface and said contact points of said wafer by moving said support and said surface into proximity; and

supplying diagnostic signals to said flexible tester surfaces for testing said electrical devices and circuitry.

11. A method of testing as in claim 10 further comprising the step of separating said wafer into a plurality of dice prior to the step of electrically interconnecting.

12. A method of testing as in claim 11, further comprising the step of completing manufacturing of an integrated circuit including a plurality of said integrated circuit logic units prior to the step of electrically interconnecting.

13. A method as in claim 10, wherein in the step of supplying, a plurality of said devices are supplied simultaneously.