Method of fabricating electronic circuitry unit containing stacked IC layers having lead rerouting

• US 5,104,820 A
• Filed: 06/24/1991
• Issued: 04/14/1992
• Est. Priority Date: 07/07/1989
• Status: Expired due to Term

• Current Assignee: Aprolase Development Co LLC (Intellectual Ventures LLC)
• Original Assignee: Irvine Sensors Corp.
• Inventors: Shanken, Stuart N., Go, deceased, Tiong C., Minahan, Joseph A.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Graybill, David E.
• Application Number:
  US07/720,025
• Time in Patent Office: 295 Days
• Field of Search: 174/52.4, 357/75, 361/395, 361/392, 361/401, 437/208, 437/51
• US Class Current: 438/109
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06593 Mounting aids permanently on device; arrangements for alignment use of temporary supports H01L21/6835
• CPC Class Codes: H01L 2225/06596 Structural arrangements for testing testing or measuring during manufacture or treatment H01L22/00; testing electrical properties or locating electrical faults G01R31/00
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A process is disclosed which applies advanced concepts of Z-technology to the field of dense electronic packages. Starting with standard chip-containing silicon wafers, modification procedures are followed which create IC chips having second level metal conductors on top of passivation (which covers the original silicon and its aluminum or other metallization). The metal of the second level conductors is different from, and functions better for electrical conduction, than the metallization included in the IC circuitry. The modified chips are cut from the wafers, and then stacked to form multi-layer IC devices. A stack has one or more access planes. After stacking, and before applying metallization on the access plane, a selective etching step removes any aluminum (or other material) which might interfere with the metallization formed on the access plane. Metal terminal pads are formed in contact with the terminals of the second level conductors on the stacked chips. The pads and terminals are formed of the same metallic material in order to maximize T-connection conducting efficiency.

Claims

1. A method of forming a dense electronic package comprising:

providing a wafer having multiple IC chips formed thereon, each chip having metallization forming I/O terminals;

adding a layer of passivation over the active surface of the wafer;

forming a plurality of second level electrical conductors on top of the passivation layer, such conductors (a) being formed of metallic material which is different from the chip metallization material, and (b) each extending between a first I/O terminal lead in contact with a chip I/O terminal and a second I/O lead terminal available for external electrical I/O connection;

cutting from the wafer a plurality of individual IC chips, each having a plurality of second level conductors and each having its second I/O terminal leads accessible for external connection;

integrating a plurality of such IC chips in a stack which has at least one access plane on which the second I/O terminal leads of the second level electrical connectors are exposed;

forming a plurality of terminal pads on the access plane, each pad (a) being in electrical contact with one of the access plane I/O terminal leads in the form of a T-shaped connection, and (b) being formed of the same metallic material as that of the electrical conductor which it contacts;

the metallic material which forms the second level electrical connectors and the terminal pads on the access plane being both (a) more chemically inert and (b) easier to process for maximum conductance at the T-shaped connections than the chip metallization material; and

then connecting the access plane terminal pads to exterior circuitry.

2. The method of claim 1 in which:

the metallic material which forms the second level conductors and their T-connection lead/pad terminals is gold.

3. The method of claim 1, which also comprises:

thickening the second level electrical conductors to substantially increase their conductance.

4. The method of claim 2, which also comprises:

forming a thin layer of an adhesive metal between each gold surface and non-gold surface, in order to provide adhesion of the non-oxidizing gold to the other surface.

5. The method of claim 4, in which:

the adhesive metal is titanium/tungsten alloy.

6. The method of claim 1, which also comprises:

removing, from the access plane of the stack, material of the IC chip edges, in such a way as to leave protruding from the access plane the metal I/O terminal leads formed by the second level electrical conductors;

selectively etching to remove any metal other than that of the second level electrical conductors; and

applying a layer of passivation to cover the access plane except where I/O terminal leads are exposed.

7. The method of claim 6, in which:

the protruding leads comprise aluminum in the original wafer and non-aluminum metal leads provided by the second level electrical conductors; and

the selective etching removes the aluminum, but not the other metal.

8. The method of claim 1 in which:

the layer of passivation added over the active surface of the wafer is silicon oxy-nitride.

9. The method of claim 8, in which:

the layer of silicon oxy-nitride is formed by plasma-enhanced chemical vapor deposition.

10. The method of claim 8 which also comprises:

adding a layer of silicon nitride passivation over the non-active surface of the wafer.

11. The method of claim 1 which also comprises:

subjecting the wafer passivation to photo-lithographic processes by which desired openings are formed through the passivation.

12. The method of claim 1 in which:

the terminal pads on the access plane which form T-shaped connections with the second level conductors are formed by means of a sputtering process.

13. The method of claim 1 in which:

the layer of passivation added over the active surface of the wafer is a polyimide material.