Level shift circuit with common mode rejection
First Claim
1. A circuit including first and second power switches that are connected with their respective current paths in series between source of a first power voltage and a source of a second power voltage where said first power switch is referenced to said first power voltage and said second power switch is referenced to a node at a junction of said current paths, said circuit preventing false operation in the presence of noise and comprising:
- means for operating said first switch in response to control pulses from a source that is referenced to said first power voltage;
a source of control pulses for controlling said second switch;
means for producing narrower pulses across respective impedances in response to the leading and trailing edges of said control pulses for said second switch, said narrower pulses being referenced to said node;
closing means for said second switch responsive to the occurrence of only said narrower pulses produced in response to said leading edges;
opening means for said second switch responsive to the occurrence of only said narrower pulses produced in response to said trailing edges; and
common mode control means responsive to the occurrence of noise voltages simultaneously across both of said impedances for disabling said closing means for said second switch and said opening means for said second switch, for preventing said second switch from changing state at the time of occurrence of the noise voltages.
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Accused Products
Abstract
A system includes an upper driver circuit connected between a first source of voltage and a first point of reference potential, for driving the gate of a first switching device having a main current path connected between a second source of operating voltage and the first point of reference potential. The system further includes a lower driver circuit connected between a third source of operating voltage and a second point of reference potential, for driving the gate of a second switching device having a main current path connected between the first and second points of reference potential. Detection circuitry is included for detecting a common-mode dv/dt induced signal to disable the sensing of valid "ON" and "OFF" signals by the upper circuit, to prevent false triggering of the upper circuit.
23 Citations
22 Claims
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1. A circuit including first and second power switches that are connected with their respective current paths in series between source of a first power voltage and a source of a second power voltage where said first power switch is referenced to said first power voltage and said second power switch is referenced to a node at a junction of said current paths, said circuit preventing false operation in the presence of noise and comprising:
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means for operating said first switch in response to control pulses from a source that is referenced to said first power voltage; a source of control pulses for controlling said second switch; means for producing narrower pulses across respective impedances in response to the leading and trailing edges of said control pulses for said second switch, said narrower pulses being referenced to said node; closing means for said second switch responsive to the occurrence of only said narrower pulses produced in response to said leading edges; opening means for said second switch responsive to the occurrence of only said narrower pulses produced in response to said trailing edges; and common mode control means responsive to the occurrence of noise voltages simultaneously across both of said impedances for disabling said closing means for said second switch and said opening means for said second switch, for preventing said second switch from changing state at the time of occurrence of the noise voltages. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for operating series switches that are referenced to different voltages for preventing false operation of at least one of the switches in the presence of noise or voltage transients, comprising the steps of:
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providing control pulses referenced to the lower voltage for both switches; controlling the switch referenced to the lower voltage with its control pulses; forming narrow pulses at the leading and trailing ends of the control pulses for the switch referenced to the higher voltage; shifting the reference level of the narrow pulses to the higher reference voltage in such manner that the narrow pulses appear across different impedances; respectively coupling the narrow pulses across said impedances that occur at the leading and trailing ends of the control pulses to set and reset inputs of a bistable device; controlling the second switch with voltages produced at the output of said bistable device; and preventing the narrow pulses across said impedances from being coupled to said set and reset inputs of said bistable device when common mode voltages appear across said impedances due to the occurrence of noise or voltage transients.
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9. A switching circuit comprising:
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a first switch referenced to a first potential; a second switch referenced to a second potential greater than said first potential; a first source of current pulses referenced to said first potential; a second source of current pulses referenced to said first potential; a source of D.C. operating potential referenced to said second potential; a first impedance connected between said source of operating potential and said first source of current pulses; a second impedance connected between said source of operating potential and said second source of current pulses; control means responsive to a voltage across said first resistor for closing said second switch; control means responsive to a voltage across said second resistor for opening said second switch; and common mode sensing means responsive to voltages simultaneously occurring across said first and second resistors for disabling both of said control means, said common mode sensing means having greater sensitivity than both of said control means.
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10. In a circuit having first and second switches connected in series between a first source of operating voltage and a first point of reference potential, the combination comprising:
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a source of control pulses; means for generating first pulses in response to the rising edges of said control pulses; means for generating second pulses in response to the trailing edges of said control pulses; a second source of operating voltage referenced to the junction of said first and second switches, said junction serving as a second point of reference potential; a first current generator and a first resistor connected in series in the order named between said first point of reference potential and said second source of operating voltage; means for coupling said first pulses to said first current generator in order to cause it to produce corresponding pulses of current through said first resistor; a second current generator and a second resistor connected in series in the order named between said first point of reference potential and said second source of operating voltage; means coupling said second pulses to said second current generator so as to cause it to produce corresponding pulses of current through said second resistor; a latch; first coupling means for coupling the first resistor so as to set said latch in response to pulses of voltage produced across first resistor by said first pulses of current flowing through it; second coupling means for coupling the second resistor so as to reset said latch in response to pulses of voltage produced across said second resistor by said second pulses of current flowing through it; and means responsive to common mode voltages appearing across said first and second resistor for preventing said first and second coupling means from respectively setting and resetting said latch. - View Dependent Claims (11)
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12. A circuit for alternately closing first and second switches of a pulsed power supply that are connected in series at a junction in the order named between ground and a power supply voltage, comprising:
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a first source of spaced switch control pulses that is referenced to ground; means for closing said first switch in response to the switch control pulses from said first source; a second source of spaced switch control pulses that is referenced to ground; a source of device operating potential referenced to said junction; a first impedance and a first current generator connected in series between said source of device operating potential an ground; a leading edge triggered one shot multivibrator coupled between said second source of switch control pulses and said first current generator so as to produce pulses of current through said first impedance in response to the leading edges of the switching pulses provided by said second source; a second impedance and a second current generator connected in series between said source of device operating potential and ground; a trailing edge triggered one shot multivibrator coupled between said second source of switch control pulses and said second current generator so as to produce pulses of current through said second impedance in response to the trailing edges of the switching pulses provided by said second source; a bistable circuit having an output; first bistable circuit control means coupled between said first impedance and said bistable circuit for putting it in a first state when a pulse of current only flows through said first impedance; second bistable circuit control means coupled between said second impedance and said bistable circuit for putting it in a second state when a pulse of current only flows through said second impedance; means for closing said second switch when said bistable circuit is in said first state and for opening it when said bistable circuit is in said second state; and common mode control means responsive to currents flowing simultaneously in said first and second impedances, due to noise or voltage transients, for disabling said first and second bistable circuit control means. - View Dependent Claims (13, 14, 15)
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16. In combination with a transistor having its conduction path coupled between a first terminal for the application thereto of a relatively high voltage (VH) and a load terminal for the connection thereto of a load, and including a second terminal for the application thereto of a relatively low operating voltage (VOP) relative to said load terminal and, further including control means connected between said load terminal and said second terminal for turning said transistor on and off in response to respective first and second control signals, the improvement comprising:
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said operating voltage (VOP) being referenced to the voltage appearing at said load terminal, for supplying power to said control means, said control means using a portion of said power from said operating voltage for turning on said transistor switch; first means connected between said second terminal and a source of reference potential for developing said first control signal at a first node during one period of time; second means connected between said second terminal and said source of reference potential for developing said second control signal at a second node during another period of time; and inhibit means included in said control means for sensing when voltages of similar value appear simultaneously at said first and second nodes, for preventing said transistor switch from changing state. - View Dependent Claims (17, 18)
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19. A control system for producing a signal at an output having a first value in response to the presence of a control signal at a first input node and having a second value in response to the presence of a control signal at a second input node, said system comprising:
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a bistable device having set and reset inputs and an output; first control means for coupling control signals from said first input node to said set input when enabled; second control means for coupling control signals from said second input node to said reset input when enabled; and third control means coupled to said first and second nodes for enabling said first and second control means when a signal appears at only one of said input nodes and for disabling said first and second control means when noise simultaneously appears at said first and second nodes, said third control means being more sensitive than said first and second control means. - View Dependent Claims (20, 21)
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22. The combination comprising:
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a first power terminal for the application thereto of a relatively high voltage (VH) relative to a point of reference potential; a transistor switch having its conduction path coupled between said first power terminal and a load terminal for driving any load connected to said load terminal towards the voltage (V ) applied at said first power terminal; control circuitry connected between the load terminal and a first voltage terminal; means for applying a first voltage to said first voltage terminal for powering the control circuitry; means coupling the control circuitry to said transistor switch for turning it on and off, said control circuitry including a first node at which is produced a turn-on signal and a second node at which is produced a turn-off signal; and means in the control circuitry for sensing when the voltages at the first and second nodes are of similar value indicative of a noise or faulty condition and for then generating an inhibit signal for preventing the transistor switch from changing state.
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Specification