High speed logic and memory family using ring segment buffer

• US 5,105,105 A
• Filed: 04/19/1991
• Issued: 04/14/1992
• Est. Priority Date: 03/21/1990
• Status: Expired due to Term

• Current Assignee: Technology Properties Limited LLC
• Original Assignee: Thunderbird Technologies Incorporated
• Inventors: Vinal, Albert W.
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): Bertelson, David R.
• Application Number:
  US07/687,756
• Time in Patent Office: 361 Days
• Field of Search: 307/443, 307/446, 307/448, 307/450, 307/451, 307/475, 307/570, 307/571, 307/576, 307/579, 307/585, 307/542, 307/544, 307/280, 307/300, 377/122-124
• US Class Current: 327/278
• CPC Class Codes: H01L 27/0716 in combination with vertical bipolar transistors and diodes, or capacitors, or resistors
• CPC Class Codes: H01L 27/11898 Input and output buffer/driver structures
• CPC Class Codes: H03K 17/567 Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
• CPC Class Codes: H03K 19/01707 in asynchronous circuits
• CPC Class Codes: H03K 19/09448 in combination with bipolar transistors [BIMOS]
• CPC Class Codes: H03K 19/0948 using CMOS or complementary insulated gate field-effect transistors
• CPC Class Codes: H03K 3/03 Astable circuits
• CPC Class Codes: H03K 3/356156 with synchronous operation

Abstract

A logic and memory family using CMOS technology operates at high speeds using a Ring Segment Buffer to couple logic gates to one another in an integrated circuit chip, and to couple memory cells to other circuits to provide shift registers, triggers, clock pulse generators and other memory related circuits. The Ring Segment Buffer comprises one or more serially connected complementary field effect transistor (FET) inverter stages, with the output of a preceding stage being connected to the input of a succeeding stage. The N-channel FET in each inverter stage has a channel width which is less than a predetermined factor (K) times the width of the N-channel of the immediately preceding stage. By maintaining the K channel width relationship, the Ring Segment Buffer can drive large capacitive loads at high speed. The Ring Segment Buffer may also provide a predetermined delay which is a function of channel length and the number of stages. For large capacitive loads, the last stage of the Ring Segment Buffer may be replaced by a bipolar transistor-FET driver in which minority carrier lifetime controlled bipolar transistors are used.

The Buffer Cell Logic and Delay Storage technology of the present invention may operate at speeds of 300 megahertz or more using conventional semiconductor fabrication processes in which conventional CMOS logic and memory technology operates at 70 megahertz or less. A fourfold speed improvement is thereby obtained.

Claims

1. A transition signal pulse generator for generating a pulse of a predetermined duration upon occurrence of a predetermined input signal transition, comprising:

a delay ring segment buffer having an input and an output, for producing said predetermined delay from said delay ring segment buffer input to said delay ring segment buffer output;

a logic gate, having a first and a second input and an output, the output of said delay ring segment buffer being connected to the first input of said logic gate; and

means for connecting an input signal to the input of said delay ring segment buffer and to said second input of said logic gate, to thereby generate a pulse of said predetermined duration at the output of said logic gate upon occurrence of a predetermined transition in the input signal.

2. The transition signal pulse generator of claim 1 wherein said logic gate comprises an AND gate and wherein said delay ring segment buffer comprises an inverting delay ring segment buffer, to thereby generate said pulse of said predetermined duration at the output of said AND gate upon occurrence of a positive transition in the input signal.

3. The transition signal pulse generator of claim 1 wherein said logic gate comprises and AND gate, and wherein said delay ring segment buffer comprises a noninverting delay ring segment buffer, and wherein said connecting means further comprises an inverter for connecting said input signal to said second input of said AND gate, to thereby generate said pulse of said predetermined duration at the output of said AND gate upon occurrence of a negative transition in the input signal.

4. The transition signal pulse generator of claim 2 wherein said inverting delay ring segment buffer comprises an odd number of serially connected complementary field effect transistor inverter stages.

5. The transition signal pulse generator of claim 3 wherein said inverting delay ring segment buffer comprises an even number of serially connected complementary field effect transistor inverter stages.

6. The transition signal pulse generator of claim 1 further comprising a ring segment buffer, the input of which is connected to the output of said logic gate.

7. The transition signal pulse generator of claim 1 wherein said logic gate comprises an AND gate.

8. The transition signal pulse generator of claim 1 wherein said logic gate comprises a NAND gate.

9. The transition signal pulse generator of claim 1 wherein said delay ring segment buffer comprises:

a plurality of serially connected complementary field effect transistor inverter stages, each of said complementary field effect transistor inverter stages comprising a serially connected N-channel field effect transistor and P-channel field effect transistor, the N-channel and P-channel field effect transistors having predetermined channel widths and channel lengths, each of said complementary field effect transistor inverter stages having an input and an output, with the output of an immediately preceding inverter stage being connected to the input of an immediately succeeding inverter stage, and the output of the last inverter stage being connected to the first input of the logic gate;

the N-channel field effect transistor in each inverter stage having a channel width which is less than a predetermined factor times the width of the N-channel of the immediately preceding inverter stage; and

the channel lengths of the field effect transistors in the inverter stages being at least a first predetermined length, to thereby produce said predetermined delay from the input of the first inverter stage to the output of the last inverter stage.