Conductivity-modulation metal oxide field effect transistor with single gate structure

• US 5,105,243 A
• Filed: 08/25/1989
• Issued: 04/14/1992
• Est. Priority Date: 02/26/1987
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Yamaguchi, Yoshihiro, Nakagawa, Akio, Watanabe, Kiminori
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): Loke, Steven
• Application Number:
  US07/399,342
• Time in Patent Office: 963 Days
• Field of Search: 357/23.4, 357/23.8, 357/38, 357/43, 357/41, 357/39
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/405 Resistive arrangements, e.g. resistive or semi-insulating field plates
• CPC Class Codes: H01L 29/7393 Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence

Abstract

There is disclosed a single-gate type conductivity-modulation field effect transistor having a first base layer, a second base layer, and a source layer formed in the second base layer. A source electrode is provided on a surface of the first base layer, for electrically shorting the second base layer with the source layer. A drain layer is provided in the first base layer surface. A drain electrode is formed on the layer surface to be in contact with the drain layer. A gate electrode is insulatively provided above the layer surface, for covering a certain surface portion of the second base layer which is positioned between the first base layer and the source layer to define a channel region below the gate electrode. A heavily-doped semiconductor layer is formed in the drain layer to have the opposite conductivity type to that of the drain layer. This semiconductor layer is in contact with the drain electrode. When the transistor is turned off, this layer facilitates carriers accumulated in the first base layer to flow into the drain electrode through the drain layer, thereby accelerating dispersion of the carriers in said transistor.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a conductivity-modulation field effect transistor formed on said substrate, said transistor having a base region of a first conductivity type, a source region of a second conductivity type formed in one portion of said base region, a source electrode for electrically connecting said base region and said source region with each other, a drain region of the first conductivity type formed in another portion of said base region, a drain electrode formed on said drain region, and a gate electrode insulatively provided above said substrate on a channel region formed between source and drain regions; and

means for, when said transistor is turned off, facilitating carriers in said device to flow into said drain electrode, thereby accelerating dispersion of the carriers in said transistor, said means comprising a first heavily-doped semiconductive layer of the second conductivity type which is formed in said drain region to have a conductivity type opposite to that of said drain region, said semiconductive layer being in contact with said drain electrode.

2. The device according to claim 1, wherein said substrate has a surface in which said base region an said drain region are formed.

3. The device according to claim 2, further comprising:

a second heavily-doped semiconductive layer which is formed in said drain region to overlap the first heavily-doped semiconductive layer, said second semiconductive layer having a conductivity type opposite to that of said first semiconductive layer.

4. The device according to claim 2, further comprising:

a second heavily-doped semiconductive layer which is formed in said drain region to be contact with said drain electrode, said second semiconductive layer having a conductivity type opposite to that of said first semiconductive layer.

5. The device according to claim 4, further comprising:

a third heavily-doped semiconductive layer having the conductivity type opposite to that of said source region and which is formed in said substrate so as to overlap said base region and said source region and to be in contact with said source electrode.

6. A single-gate type conductivity-modulation field effect transistor comprising:

a first base layer having a surface;

a second base layer of a first conductivity type provided in the surface of said first base layer;

a source layer provided in said second base layer;

a source electrode provided on the layer surface, for electrically shorting said second base layer with said source layer;

a drain layer having said first conductivity type provided in said layer surface;

a drain electrode formed on said layer surface to be in contact with said drain layer;

a gate electrode insulatively provided above said layer surface, for covering a certain surface portion of said second base layer which is positioned between said first base layer and said source layer to define a channel region below said gate electrode; and

a heavily-doped semiconductor layer of a second conductivity type which is provided in a selected surface portion of said drain layer and which is included in said drain layer to be in contact with said drain electrode, said heavily-doped semiconductor layer facilitating, when said transistor is turned off, carriers accumulated in said first base layer to flow into said drain electrode through said drain layer, thereby accelerating dispersion of the carriers in said transistor; and

wherein said first base layer and said source layer have said second conductivity type.

7. The transistor according to claim 6, wherein said drain layer comprises heavily-doped drain layer portions each pair of two adjacent layer portions of which are separated from each other.

8. The transistor according to claim 7, wherein said source layer has one side portion along which a plurality of projected layer portions are aligned to define a comb-shaped planar pattern.

9. The transistor according to claim 6, further comprising:

a high-resistive layer insulating provided above said layer surface and connected with said source electrode and said drain electrode.

10. The transistor according to claim 6, wherein said drain layer comprises:

a first diffusion layer; and

a second diffusion layer which at least partially surrounds said heavily doped semiconductor layer and which has its depth smaller than that of said first diffusion layer, said second diffusion layer formed adjacent said first diffusion layer.

11. The transistor according to claim 10, further comprising:

a second heavily doped semiconductor layer of a conductivity type which is the same of that of said drain layer and which is formed in said first diffusion layer.

12. The transistor according to claim 11, wherein said second heavily doped semiconductor layer is in contact with said drain electrode.