Idling system for devices having speed controllers

• US 5,105,331 A
• Filed: 01/18/1990
• Issued: 04/14/1992
• Est. Priority Date: 01/18/1990
• Status: Expired due to Fees

• Current Assignee: Briggs & Stratton Corporation
• Original Assignee: Briggs & Stratton Corporation
• Inventors: Dykstra, Richard A., Fiorenza, John A. II
• Primary Examiner(s): Pellinen, A. D.
• Assistant Examiner(s): Gaffin, Jeffrey A.
• Application Number:
  US07/466,781
• Time in Patent Office: 817 Days
• Field of Search: 361/236, 361/239, 361/240, 361/242, 123/339
• US Class Current: 361/236
• CPC Class Codes: F02D 41/0205 using an auxiliary engine speed control engine speed control per se F02D31/00
• CPC Class Codes: F02D 41/083 taking into account engine load variation, e.g. air-conditionning

Abstract

An idling system is disclosed for devices such as internal combustion engines having a speed controlling or governor. When no load is sensed by a load sensing means, a disable means generates a disable signal to deactivate the engine'"'"'s speed controller after a predetermined time delay period. When a load is sensed, the disable means is itself disabled, allowing the device'"'"'s speed control means to operate the device at the higher governed speed.

Claims

1. An idling system for use with a device that powers a load, said device having a speed control means for adjusting the speed of the device and also having a load sensing means for sensing whether a load is applied to said device and for outputting a load sensing signal when a load is so applied, said idling system comprising:

disable means for outputting a disable signal to said speed control means to disable said speed 10 control means after a time delay period when said load sensing means senses that no load is being applied to said device, and for activating said speed control means by ceasing the outputting of said disable signal when said load sensing means senses that a load is being applied to said device; and

time delay means for delaying the outputting of said disable signal to said speed control means for said time delay period.

2. The idling system of claim 1, wherein said time delay means includes:

clock means for outputting a periodic clock signal to said disable means.

3. The idling system of claim 1, wherein said time delay means includes:

input means for receiving a periodic clock signal; and

at least one frequency divider means for frequency dividing said periodic clock signal and outputting a divided frequency signal after said time delay period to said disable means.

4. The idling system of claim 3, wherein said frequency divider means includes a flip-flop.

5. The idling system of claim 3, wherein said disable means includes a multiple input gate that receives as its inputs a signal functionally related to said load sensing signal and also receives said divided frequency signal, and which outputs said disable signal.

6. The idling system of claim 5, further comprising:

starting means for disabling the disable means until the device reaches a predetermined minimum speed, said starting means including;

means for outputting a low speed signal when the speed of the device is below the predetermined minimum speed; and

an OR gate having the low speed signal as an input and whose output resets said frequency divider to prevent said frequency divider from outputting a divided frequency signal.

7. The idling system of claim 1, wherein said disable means includes a multiple input gate.

8. The idling system of claim 1, further comprising:

starting means for disabling the disable means until the device reaches a predetermined minimum speed.

9. The idling system of claim 8, wherein said starting means includes:

means for outputting a low speed signal when the speed of the device is below the predetermined minimum speed; and

an OR gate having the low speed signal as an input and whose output disables said disable means.

11. The idling system of claim 1, wherein said time delay means includes:

input means for receiving a periodic signal from said device; and

a capacitor that is charged by said periodic signal.

12. The idling system of claim 11, wherein said periodic signal is related to the speed of said device.

13. The idling system of claim 12, wherein said periodic signal represents at least one revolution of said device.

14. The idling system of claim 12, wherein said periodic signal is a square wave in which each pulse represents a single revolution of said device.

15. The idling system of claim 1, wherein said disable means includes a switch that is activated in response to said time delay means to output said disable signal.

16. The idling system of claim 1, wherein said disable means includes:

a full-wave rectifier that rectifies said load sensing signal;

a capacitor that is charged by said rectified load sensing signal; and

a switch which is activated when said capacitor is charged to prevent said disable means from outputting said disable signal to the speed control means.

17. An idling system for use with a device that powers a load, said device having a speed control means for adjusting the speed of the device and also having a load sensing means for sensing whether a load is applied to the device and for outputting a load sensing signal when a load is so applied, said idling system comprising:

disable means for outputting a disable signal to said speed control means to disable said speed control means after a time delay period when said load sensing means senses that no load is being applied to said device, and for ceasing the outputting of said disable signal to activate said speed control means when said load sensing means senses that a load is being applied to said device, said disable means including

a multiple-input gate that receives as its inputs a signal functionally related to said load sensing signal and also receives a divided frequency signal after a time delay period, and which outputs said disable signal; and

time delay means for outputting said divided frequency signal after said time delay period to said multiple-input gate.

18. The idling system of claim 17, wherein said time delay means includes:

input means for receiving a periodic clock signal; and

at least one frequency divider means for frequency dividing said periodic clock signal and outputs a divided frequency signal after said time delay period to said gate.

19. The idling system of claim 17, further comprising:

starting means for disabling the disable means until the device reaches a predetermined minimum speed.

20. An idling system for use with a device that powers a load, said device having a speed control means for adjusting the speed of the device and also having a load sensing means for sensing whether a load is applied to said device and for outputting a load sensing signal when a load is so applied, said idling system comprising:

disable means for outputting a disable signal to said speed control means to disable said speed control means after a time delay period when said load sensing means senses that no load is being applied to said device;

time delay means for delaying the outputting of said disable signal to said speed control means for a time delay period; and

activation means for activating said speed control means when said load sensing means senses that a load is being applied to said device.

10. The idling system of claim 21, further comprising:

a resistor that enables said capacitor to fully discharge after said device stops operating.

21. The idling system of claim 20, wherein said time delay means includes:

input means for receiving a periodic signal from said device; and

a capacitor that is charged by said periodic signal.

22. The idling system of claim 21, wherein said periodic signal is related to the speed of said device.

23. The idling system of claim 22, wherein said periodic signal represents at least one revolution of said device.

24. The idling system of claim 22, wherein said periodic signal is a square wave in which each pulse represents a single revolution of said device.

25. The idling system of claim 20, wherein said activation means includes:

a full-wave rectifier that rectifies said load sensing signal;

a capacitor that is charged by said rectified load sensing signal; and

a switch which is activated when said capacitor is charged to prevent said disable means from outputting said disable signal to the speed control means.

26. The idling system of claim 25, further comprising:

conditioning means for conditioning said load sensing signal.