Process for manufacturing vertical dynamic random access memories

• US 5,106,775 A
• Filed: 07/30/1990
• Issued: 04/21/1992
• Est. Priority Date: 12/10/1987
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Kaga, Toru, Kawamoto, Yoshifumi, Sunami, Hideo
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US07/564,470
• Time in Patent Office: 631 Days
• Field of Search: 437/47, 437/48, 437/51, 437/52, 437/60, 437/62, 437/69, 437/70, 437/84, 437/89, 437/203, 437/228, 437/233, 437/235, 437/238, 437/249, 357/23.6, 357/51
• US Class Current: 438/155
• CPC Class Codes: H01L 21/28211 in a gaseous ambient using an oxygen or a water vapour, e.g. RTO, possibly through a layer H01L21/28194 and H01L21/28202 take precedence
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body
• CPC Class Codes: H01L 29/51 Insulating materials associated therewith for MIS structures on thin film semiconductor H01L29/4908
• CPC Class Codes: H01L 29/66181 Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/0383 wherein the transistor is vertical
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

A semiconductor memory comprises a switching device and a charge-storage device disposed at the upper and lower sides, respectively, of each of semiconductor islands. The islands are formed on a semiconductor substrate that is completely isolated from the semiconductor substrate by an insulator. The switching device and charge-storage device are substantially the same width. The memory cell structure is extremely small. The cell structure is highly resistant to alpha-particles and is formed self-aligned. During manufacture, the SiO₂ island is oxidized adjacent its lower end to insulate the island from the substrate.

Claims

1. A method for forming a semiconductor islands memory, the method comprising:

forming a plurality of semiconductor islands isolated from each other at regular spacings on and isolated from a semiconductor substrate, with each semiconductor island having an upper part and a lower part in which a switching device and a charge storage device are formed, totally isolated from the substrate the upper and lower parts having substantially the same width.

2. A method for making a semiconductor memory that includes a plurality of a switching devices and charge storage devices, the method comprising:

forming a plurality of semiconductor islands of a first conductivity type that are isolated from each other on a semiconductor substrate, each of the islands having a lower part toward the substrate and an upper part away from the substrate, the upper part being substantially the same width as the lower part;

insulating the semiconductor islands from the semiconductor substrate;

forming a doped impurity layer of a second conductivity type opposite to the first conductivity type in a surface region of at least a side wall of the lower part of each semiconductor island;

forming an electrode on a capacitor insulator along a surface of the impurity doped layer.

3. A method of manufacturing a semiconductor integrated circuit comprising:

on a semiconductor substrate, forming a plurality of semiconductor islands which are isolated from the semiconductor substrate and each other by insulator means, each semiconductor island having a lower side closer to the substrate and an upper side further from the substrate;

forming a switching device and a charge storage device on the upper and lower sides of each of a plurality of the semiconductor islands, the width of the upper side of the semiconductor islands having substantially the same width as the lower side, wherein said switching device and change storage device are totally isolated from the substrate.

4. A process for producing a semiconductor memory comprising:

a) depositing a first antioxidation film on a semiconductor substrate and then anisotropic etching said first antioxidation film and the semiconductor substrate to form a semiconductor island having said first antioxidation film on its upper end;

b) depositing a second antioxidation film on said semiconductor substrate and said semiconductor island and then anisotropic etching to leave said . second antioxidation film on the sidewall of said semiconductor island, and further anisotropic etching using as masks said first and second antioxidation films left on the upper end and sidewall of said semiconductor island for further etching said semiconductor substrate;

c) depositing a third antioxidation film on said semiconductor substrate and said semiconductor island and then anisotropic etching to leave said third antioxidation film on the sidewall of said semiconductor island; and

,

d) oxidizing the surface of said semiconductor substrate using said first, second, and third antioxidation films as masks to form an insulator which isolates the semiconductor island from said semiconductor substrate.

5. The process for producing a semiconductor memory according to claim 4 further comprising between steps (c) and (d), isotropic etching using said first, second, and third antioxidation films as masks to narrow a bottom portion of said semiconductor island.

6. The process for producing a semiconductor memory according to claim 4 further comprising:

e) partially removing after said step (d), said antioxidation film and then forming an impurity doped layer on the surface of the sidewall of a lower part of said semiconductor island, said impurity doped layer being of a second conductivity type which is opposite to a first conductivity type which is opposite to a first conductivity of an impurity contained in said semiconductor island;

f) forming a capacitor insulator on the surface of said impurity doped layer;

g) depositing a first conductive film and then isotropic etching to form a capacitor electrode on said insulator, said capacitor electrode being in contact with said capacitor insulator;

h) forming a second insulator on said first conductive film;

i) depositing a second conductive film and then anisotropic dry etching such that said conductive film is left on the sidewall of an upper part of said semiconductor island;

j) removing said first antioxidation film from the upper end surface of said semiconductor island, forming a third insulator on the upper end surface of said semiconductor island, and then forming an impurity doped layer of said second conductivity type on the upper end surface of said semiconductor island;

k) depositing a fourth insulator on said second insulator;

l) forming an opening in said fourth insulator on said semiconductor island and then forming a conductive film at least partially therein.

7. The process for producing a semiconductor memory according to claim 6 further comprising:

removing, between said steps (h) and (i), said second and third antioxidation films and then forming a gate insulator on the surface of the sidewall of said semiconductor island.

8. A process for producing a semiconductor memory comprising:

a) depositing a first antioxidation film on a semiconductor substrate and then anisotropic etching said first antioxidation film and the semiconductor substrate to form a semiconductor island having said first antioxidation film mounted on its upper end;

b) depositing a second antioxidation film on said semiconductor substrate and said semiconductor island and then anisotropic etching to leave said second antioxidation film on a sidewall of said semiconductor island, and further anisotropic etching using as masks said first and second antioxidation films left on the upper end and sidewall of said semiconductor island for further etching said semiconductor substrate;

c) depositing a third antioxidation film on said semiconductor substrate formed with said semiconductor island and then anisotropic etching to leave said third antioxidation film on the sidewall of said semiconductor island; and

,

d) oxidizing the surface of said semiconductor substrate using said first, second, and third antioxidation films as masks to form an insulator which isolates the semiconductor island from said semiconductor substrate;

e) partially removing said antioxidation film and then forming an impurity doped layer on the surface of the sidewall of the lower part of said semiconductor island, said impurity doped layer being of a second conductivity type which is opposite to a first conductivity type of an impurity contained in said semiconductor island;

f) forming a capacitor insulator on the surface of said impurity doped layer;

g) depositing a conductive film and then carrying out isotropic etching as far as a desired position from the surface to form a capacitor electrode on said insulator, said capacitor electrode being in contact with said capacitor insulator;

h) forming a second insulator on said conductive film;

i) depositing a conductive film and then carrying out anisotropic dry etching such that said conductive film is left on the sidewall of the upper part of said semiconductor island;

j) removing said antioxidation film from the upper end surface of said semiconductor island, forming a third insulator on the upper end surface of said semiconductor island, and then forming an impurity doped layer of said second conductivity type on the upper end surface of said semiconductor island;

k) depositing a fourth insulator on said second insulator; and

,

l) forming an opening in said fourth insulator on said semiconductor island and then forming a conductive film.

9. The process for producing a semiconductor memory according to claim 8 further comprising:

between said steps (h) and (i), removing said antioxidation film and then forming a gate insulator on a surface of the sidewall of said semiconductor island.

10. A process for producing a semiconductor memory according to claim 8 further comprising:

between said steps (c) and (d), isotropic etching using said first, second, and third antioxidation films as masks to narrow a bottom portion of said semiconductor island.