Vertical transistor device fabricated with semiconductor regrowth

• US 5,106,778 A
• Filed: 02/16/1990
• Issued: 04/21/1992
• Est. Priority Date: 02/02/1988
• Status: Expired due to Fees

• Current Assignee: Massachusetts Institute of Technology
• Original Assignee: Massachusetts Institute of Technology
• Inventors: Bergeron, Normand J. Jr., Hollis, Mark A., Bozler, Carl O., Nichols, Kirby B.
• Primary Examiner(s): Saba, William G.
• Application Number:
  US07/481,860
• Time in Patent Office: 795 Days
• Field of Search: 148/DIG. 26, 148/DIG. 50, 148/DIG. 88, 148/DIG. 142, 437/84, 437/90, 437/175, 437/911, 156/643, 156/644, 156/653, 156/657, 357/15, 357/22 E, 357/22 C, 357/22 D, 357/22 I, 357/55
• US Class Current: 438/173
• CPC Class Codes: H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268 etching for patterning the electrodes H01L21/311, H01L21/3213; multistep manufacturing processes for data storage electrodes H01L29/4011
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/66454 Static induction transistors [SIT], e.g. permeable base transistors [PBT]
• CPC Class Codes: H01L 29/66856 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/7722 using static field induced regions, e.g. SIT, PBT
• CPC Class Codes: H01L 29/8122 Vertical transistors SIT, PBT H01L29/7722
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: Y10S 148/026 Deposition thru hole in mask
• CPC Class Codes: Y10S 148/05 Etch and refill
• CPC Class Codes: Y10S 148/088 J-Fet, i.e. junction field effect transistor
• CPC Class Codes: Y10S 148/142 Semiconductor-metal-semiconductor

Abstract

A vertical transistor device is characterized by active regions vertically separated by a narrower control region. The control region is defined by conducting layer extensions which extend into a groove within which semiconductor material is regrown during device fabrication. The device is further characterized by regions of isolating material, located horizontally adjacent to the active regions, said isolating material serving to reduce parasitic capacitance and improve thermal distribution within the device, thereby improving frequency and power performance.

Claims

1. A method of fabricating a transistor device of the type comprising a single type of semi-conductor material divided into active regions by a control region, the method comprising:

providing a contact layer;

forming a first isolation layer on a surface of the contact layer;

providing a conducting layer on a surface of the first isolation layer;

removing material from the layered article to provide a groove through the conducting and isolation layers, thereby exposing the contact layer surface;

removing isolation material from at least one sidewall of the groove, thereby allowing the conducting layer to extend beyond the isolation material; and

growing a semiconductor crystal within the groove past the conducting layer to form the active regions and the control region.

2. A method as in claim 1 further comprising the step of forming a second isolation layer on a surface of the conducting layer before the steps of removing material.

3. A method as in claim 1 wherein the conducting layer extends beyond the isolation material to a distance on the order of the zero bias depletion width of the semiconductor.

4. A method as in claim 1 wherein the isolation layer is selected from the group consisting of silicon dioxide and silicon nitride.

5. A method as in claim 1 wherein the conducting layer is selected from the group consisting of tungsten and doped poly-silicon.

6. A method as in claim 1 wherein the contact layer comprises a conducting material.

7. A method as in claim 1 wherein the contact layer comprises a heavily doped, epitaxial semiconductor layer deposited upon a base layer.

8. A method as in claim 7 wherein the base layer is selected from the group consisting of III-V materials and group IV materials.

9. A method as in claim 7 wherein the epitaxial layer comprises a doped III-V material.

10. A method as in claim 9 wherein the epitaxial layer comprises n⁺ GaAs.

11. A method as in claim 7 wherein the semiconductor material grown within the groove comprises the same material as that of the epitaxial layer.

12. A method as in claim 11 wherein the semiconductor material grown within the groove is doped to a lesser degree than the material of the epitaxial layer.

13. A method as in claim 1 wherein the semiconductor material grown within the groove comprises the same material as the contact layer.

14. A method as in claim 13 wherein the semiconductor crystal grown within the groove is doped.

15. A method as in claim 1 wherein the groove is formed by removing isolation and conducting material using a high resolution etching process.

16. A method as in claim 2 wherein the steps of removing material comprise the steps of:

a. patterning the surface of the second isolation layer with a removable material;

b. angle depositing a metallic, etch-resistant layer upon the patterned surface in a manner such that the removable material shadows regions of the layered article to be etched from the metallic deposition;

c. performing a reactive ion etching to remove layers of conducting and isolation material not underlying the metallic, etch-resistant pattern; and

d. removing the metallic, etch-resistant pattern and the removable material.

17. A method as in claim 16 wherein CF₄ plasma is used in the reactive ion etching.

18. A method as in claim 16 wherein the metallic pattern comprises nickel.

19. A method as in claim 16 wherein the removable material comprises polymethylmethacrylate.

20. A method as in claim 1 wherein the isolation material is removed using a wet-etch process or a CF₄ plasma etch process.

21. A method as in claim 20 wherein the wet-etch is performed using a dilute HF acid solution.

22. A method as in claim 1 wherein semiconductor crystal growth within the groove is performed using vapor phase or molecular beam epitaxy.

23. A method as in claim 1 wherein semiconductor crystal growth within the groove is performed using organometallic chemical vapor deposition.

24. A method as in claim 1 further comprising the step of removing at least some of the material which comprises at least one isolation layer subsequent to the growth of the semiconductor crystal within the groove.

25. A method as in claim 24 wherein the isolation layer from which material is removed is subsequently filled with an isolation material selected from the group consisting of air and foamed polymeric materials.