Linear, continuous-time, two quadrant multiplier
First Claim
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1. A linear, two-quadrant multiplier circuit, including:
- a first input node,an output node,a current load connected to said output node,a first voltage rail connected to a source of a first electrical potential,a second voltage rail connected to a source of a second electrical potential more negative than said first electrical potential,a first P-channel MOS transistor, having its gate connected to a second input node, and its drain connected to said output node,a second P-channel MOS transistor, having its gate connected to said second input node, and its source connected to said output node,a third P-channel MOS transistor, having its gate connected to said input node, its drain connected to the source of said first P-channel MOS transistor, and its source connected to said first voltage rail,an N-channel MOS transistor, having its gate connected to said input node, its drain connected to the drain of said second P-channel MOS transistor, and its source connected to said second voltage rail,the sizes of said third P-channel MOS transistor and said N-channel MOS transistor being chosen such that the quadratic dependance of the current through said third P-channel MOS transistor balances the quadratic dependance of the current through said N-channel MOS transistor and both said third P channel MOS transistor and said N-channel MOS transistor being operated above threshold and in saturation.
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Abstract
A linear voltage-to-current converter (LVCC) circuit includes two transistors, one P-channel and one N-channel. The input voltage is applied to the gates of both transistors. The drains of the two transistors are connected. The source of the p-type transistor is connected to a first voltage rail, and the source of the N-channel is connected to a second voltage rail of lower voltage. The output is the difference between the current through the P-channel transistor and the N-channel transistor. A linear current-to-voltage converter (LCVC) circuit is similar to the LVCC circuit, except that the gates of the transistors are tied to the drains of the transistors. The input current is supplied to the drains, and the output voltage is the voltage of the drains.
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Citations
3 Claims
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1. A linear, two-quadrant multiplier circuit, including:
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a first input node, an output node, a current load connected to said output node, a first voltage rail connected to a source of a first electrical potential, a second voltage rail connected to a source of a second electrical potential more negative than said first electrical potential, a first P-channel MOS transistor, having its gate connected to a second input node, and its drain connected to said output node, a second P-channel MOS transistor, having its gate connected to said second input node, and its source connected to said output node, a third P-channel MOS transistor, having its gate connected to said input node, its drain connected to the source of said first P-channel MOS transistor, and its source connected to said first voltage rail, an N-channel MOS transistor, having its gate connected to said input node, its drain connected to the drain of said second P-channel MOS transistor, and its source connected to said second voltage rail, the sizes of said third P-channel MOS transistor and said N-channel MOS transistor being chosen such that the quadratic dependance of the current through said third P-channel MOS transistor balances the quadratic dependance of the current through said N-channel MOS transistor and both said third P channel MOS transistor and said N-channel MOS transistor being operated above threshold and in saturation.
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2. A linear, continuous-time, two-quadrant multiplier circuit, including:
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a first input node for a first input voltage, a second input node for a second input voltage, a floating node, an output node, a current load connected to said output node, a first voltage rail connected to a source of a first electrical potential, a MOS transistor of a first conductivity type, having its gate connected to said floating node, its drain connected to said output node, and its source connected to said first voltage rail, a MOS transistor of a second conductivity type, having its gate connected to said floating node, its drain connected to said output node, and its source and substrate connected to said second input node, a first capacitor connected between said first input node and said floating node, a second capacitor connected between said second input node and said floating node, the sizes of said MOS transistors being chosen such that the quadratic dependance of the current through said MOS transistor of said first conductivity type balances the quadratic dependance of the current through said MOS transistor of said second conductivity type and both said MOS transistors being operated above threshold and in saturation.
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3. A linear, continuous-time, two-quadrant multiplier circuit, including:
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a first input node for a first input voltage, a second input node for a second input voltage, a floating node, an output node, a current load connected to said output node, a first voltage rail connected to a source of a first electrical potential, a MOS transistor of a first conductivity type, having its gate connected to said floating node, its drain connected to said output node, and its source connected to said first voltage rail, a MOS transistor of a second conductivity type, having its gate connected to said floating node, its drain connected to said output node, and its source and substrate connected to said second input node, a first capacitor connected between said first input node and said floating node, a second capacitor connected between said second input node and said floating node, the sizes of said MOS transistors being chosen such that the quadratic dependance of the current through said MOS transistor of said first conductivity type balances the quadratic dependance of the current through said MOS transistor of said second conductivity type and both said MOS transistors being operated above threshold and in saturation, means for injecting electrons onto said floating node, and means for removing electrons from said floating node.
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Specification
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Current AssigneeSynaptics Incorporated
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Original AssigneeSynaptics Incorporated
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InventorsGribble, Glenn E., Platt, John C., Mead, Carver A., Wall, Michael F.
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Primary Examiner(s)Miller, Stanley D.
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Assistant Examiner(s)Tran, Sinh N.
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Application NumberUS07/746,960Time in Patent Office246 DaysField of Search328/160, 307/529, 307/490, 307/571, 307/584, 307/585, 307/582, 307/500, 307/501, 307/498US Class Current327/357CPC Class CodesH03F 2203/30006 the push and the pull stage...H03F 2203/30009 the push and pull stages of...H03F 2203/30084 the pull circuit of the SEP...H03F 2203/30117 the push circuit of the SEP...H03F 3/3001 with field-effect transistorsH03F 3/3022 CMOS common source output S...
