Integratable phase-locked loop

• US 5,107,227 A
• Filed: 05/15/1990
• Issued: 04/21/1992
• Est. Priority Date: 02/08/1988
• Status: Expired due to Term

• Current Assignee: Magellan Corporation (Australia) Pty. Ltd.
• Original Assignee: Magellan Corporation (Australia) Pty. Ltd.
• Inventors: Brooks, David R.
• Primary Examiner(s): Pascal, Robert J.
• Application Number:
  US07/499,308
• Time in Patent Office: 707 Days
• Field of Search: 331/1 A, 331/8, 331/14, 331/17, 331/25
• US Class Current: 331/8
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/099 concerning mainly the controlled oscillator of the loop

Abstract

An integratable phase locked loop (IPLL) comprising sampled data filter means adapted to receive a first reference signal, the filter means sampling the first reference signal (Ref In) to provide a second reference signal (Control Volts Out), and voltage or current controlled oscillator (VCO) means adapted to receive said second reference signal, the second signal serving to regulate the frequency of oscillation of the oscillator, the oscillator providing as an output a digital signal which is fed back to the filter means to provide a clock signal (CLK) for said sampling.

Claims

1. A totally integratable phase locked loop (IPLL) comprising

sampled data filter means adapted to receive a first reference signal, the filter means sampling the first reference signal to provide a second reference signal,

voltage or current controlled oscillator means (VCO) adapted to receive said second reference signal, the second signal serving to regulate the oscillation frequency of the oscillator means, the oscillator means providing an output digital signal which is fed back to the filter means to provide a clock signal for said sampling, and

calibrator means inter-coupling the filter means and the oscillator means, the calibrator means serving to set gain or bias for determining output/input characteristic of the oscillator means.

3. An IPLL as claimed in claim 1 or 2, wherein the filter means stroboscopically samples the first reference signal.

4. An IPLL as claimed in claim 1 or 2 or 3, being fabricated using substantially MOS technology.

5. An IPLL as claimed in claim 1 or 2, further comprising counter or divider means adapted to receive the digital signal and provide to the filter means a divided or multiplied clock signal, the IPLL providing a multiplied frequency output from the VCO.

6. An IPLL as claimed in claim 1 or 2, being adapted for operation at low or moderate frequencies.

7. An IPLL as claimed in claim 1 or 2, wherein the second reference signal is a substantially spectrally pure (single frequency) output signal.

2. An integratable phase locked loop (IPLL) comprising sampled data filter means adapted to receive a first reference signal, the filter means including a switched capacitor filter (SCF), the filter means sampling the first reference signal to provide a second reference signal,

voltage or current controlled oscillator means (VCO) adapted to receive said second reference signal, the second signal serving to regulate the oscillation frequency of the oscillator means, the oscillator means providing an output digital signal which is fed back to the filter means to provide a clock signal for said sampling, and

calibrator means inter-coupling the filter means and the oscillator means, the calibrator means serving to set gain or bias for determining output/input characteristic of the oscillator means.

8. An integratable phase locked loop (IPLL) comprising sampled data filter means adapted to receive a first reference signal, the filter means sampling the first reference signal to provide a second reference signal,

voltage or current controlled oscillator means (VCO) adapted to receive said second reference signal, the second signal serving to regulate the oscillation frequency of the oscillator means, the oscillator means providing an output digital signal which is fed back to the filter means to provide a clock signal for said sampling, and

calibrator means inter-coupling the filter means and the oscillator means, the calibrator means serving to set gain or bias for determining output/input characteristic of the oscillator means, wherein the calibrator means includes at least one digital to analogue converter and further wherein the characteristic of the VCO is determined over the range operating frequencies of the IPLL.

9. An IPLL as claimed in claim 8, wherein the calibrator means includes two digital to analogue converters, one of which is adapted to set the gain, the other of which is adapted to set the bias.

10. An IPLL as claimed in claim 8 or 9, wherein the calibrator means further includes a register adapted to multiply the second reference signal by a constant.

11. An integratable phase locked loop (IPLL) comprising sampled data filter means adapted to receive a first reference signal, the filter means sampling the first reference signal to provide a second reference signal,

voltage or current controlled oscillator means (VCO) adapted to receive said second reference signal, the second signal serving to regulate the oscillation frequency of the oscillator means, the oscillator means providing an output digital signal which is fed back to the filter means to provide a clock signal for said sampling, and

calibrator means inter-coupling the filter means and the oscillator means, the calibrator means serving to set gain or bias for determining output/input characteristic of the oscillator means, wherein capacitor/switch pairs are provided in association with the VCO in order to influence the characteristic of the VCO.

12. An integratable phase locked loop (IPLL) comprising sampled data filter means adapted to receive a first reference signal, the filter means including a switched capacitor filter (SCF), the filter means sampling the first reference signal to provide a second reference signal,

voltage or current controlled oscillator means (VCO) adapted to receive said second reference signal, the second signal serving to regulate the oscillation frequency of the oscillator means, the oscillator means providing an output digital signal which is fed back to the filter means to provide a clock signal for said sampling, and

calibrator means inter-coupling the filter means and the oscillator means, the calibrator means serving to variably set slope and gain or bias for determining output/input characteristic of the oscillator means.