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Asynchronous/synchronous pipeline dual mode memory access circuit and method

  • US 5,107,465 A
  • Filed: 09/13/1989
  • Issued: 04/21/1992
  • Est. Priority Date: 09/13/1989
  • Status: Expired due to Term
First Claim
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1. An apparatus for selectively switching a memory address buffer in a pipeline memory access circuit between an asynchronous and a synchronous mode of operation is response to an enable control signal having a first and a second logical level, respectively, said buffer having a first and a second pass gate, each of said pass gates having a first and a second CMOS transistor, said apparatus comprising:

  • a first input for receiving clock signals;

    a second input for receiving said enable control signal;

    a first output coupled to the gate of the first transistor in each of said first and second pass gates;

    a second output coupled to the gate of the second transistor in each of said first and second pass gates; and

    means responsive to said clock signals on said first input and said enable control signal on said second input for providing complementary clock signals on said first and said second outputs, respectively, so as to make conductive the transistors in one of said first and second pass gates while making non-conductive the transistors in the other of said first and second pass gates when said enable control signal is at its first logical level, and a pass gate control signal having the same logical level on both said first and said second outputs for making conductive at least one transistor in each of said first and second pass gates when said enable control signal is at its second logical level.

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