Method for interconnecting a stack of integrated circuits at a very high density

• US 5,107,586 A
• Filed: 03/15/1991
• Issued: 04/28/1992
• Est. Priority Date: 09/27/1988
• Status: Expired due to Term

• Current Assignee: Lockheed Martin Corporation (Martin Marietta Corporation)
• Original Assignee: General Electric Company
• Inventors: Eichelberger, Charles W., Wojnarowski, Robert J.
• Primary Examiner(s): Arbes, Carl J.
• Application Number:
  US07/669,706
• Time in Patent Office: 410 Days
• Field of Search: 437/208, 437/209, 437/211, 437/220, 361/396, 361/412, 29/825, 29/830, 29/840
• US Class Current: 29/830
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/451 with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 23/32 Holders for supporting the complete device in operation, i.e. detachable fixtures H01L23/40 takes precedence
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01039 : Yttrium [Y]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/30107 : Inductance
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: Y10T 29/49126 : Assembling bases
• CPC Class Codes: Y10T 29/49144 : by metal fusion

Abstract

Interconnected integrated cirucits (16) packaged at a very high density are fabricated beginning with a plurality of substrates (50 or 400 or 500) where each substrate has metal edge contact sites (12 or 507). Several substrates are joined together in a stack (82 or 402 or 512) held together tightly by bolts (62) or by a thermoplastic adhesive (510). An interconnect pattern (250 or 423) electrically connects integrated circuits (16) on different substrates. Defective substrates are removable from the stack for repair by removing the bolts or by heating the adhesive to soften it sufficiently to allow removal of the individual substrate. The interconnect pattern, which is removed whenever a substrate is replaced, is reapplied after the removed substrate has been replaced.

Claims

1. A method for interconnecting integrating circuits at a very high density, comprising the steps of:

fabricating a plurality of substrates, each respective substrate having an integrated circuit thereon and edge contact pads at an edge thereof, and on each respective substrate said integrated circuit and said edge contact pads being electrically connected;

coating a top and bottom surface of each of said substrates, respectively, with an adhesive;

stacking said substrates in a vertical configuration such that for any adjacent pair of substrates said adhesive bonds the top surface of one substrate to the bottom surface of the other substrate so as to form a unitary stacked module;

laminating a dielectric layer to a side of said stacked module;

forming apertures through said dielectric layer to said edge contact pads on said substrates in said stacked module by laser dithering holes through said dielectric layer; and

creating an interconnect pattern on said dielectric layer, said interconnect pattern being electrically connected to said edge contact pads through said apertures in said dielectric layer, said interconnected pattern electrically interconnecting in a predetermined manner the integrated circuits on said substrates in said stacked module.

2. A method for interconnecting integrated circuits at a very high density, comprising the steps of:

fabricating a plurality of substrates, each respective substrate having an integrated circuit thereon and edge contact pads at an edge thereof, and on each respective substrate said integrated circuit and said edge contact pads being electrically connected;

coating a top and bottom surface of each of said substrates, respectively, with an adhesive;

stacking said substrates in a vertical configuration such that for any adjacent pair of substrates said adhesive bonds the top surface of one substrate to the bottom surface of the other substrate so as to form a unitary stacked module;

spraying an adhesive onto a side of said stacked module and then applying a dielectric film under pressure to said side of said stacked module so as to thereby laminate a dielectric layer to said side of said stacked module;

forming apertures through said dielectric layer to said edge contact pads on said substrates in said stacked module; and

creating an interconnect pattern on said dielectric layer, said interconnect pattern being electrically connected to said edge contact pads through said apertures in said dielectric layer, said interconnect pattern electrically interconnecting in a predetermined manner the integrated circuits on said substrates in said stacked module.

3. A method for interconnecting integrated circuits at a very high density, comprising the steps of:

fabricating a plurality of substrates, each respective substrate having an integrated circuit thereon and edge contact pads at an edge thereof, and on each respective substrate said integrated circuit and said edge contact pads being electrically connected;

coating a top and bottom surface of each of said substrates, respectively, with an adhesive;

stacking said substrates in a vertical configuration such that for any adjacent pair of substrates said adhesive bonds the top surface of one substrate to the bottom surface of the other substrate so as to from a unitary stacked module;

laminating a dielectric layer to said edge contact pads on said substrates in said stacked module; and

creating an interconnect pattern on said dielectric layer, said interconnect pattern being electrically connected to said edge contact pads through said apertures in said dielectric layer, said interconnect pattern electrically interconnecting in a predetermined manner the integrated circuits on said substrates in said stacked module wherein the step of creating an interconnect pattern comprises the steps of;

applying a metal layer on said dielectric layer;

coating over said metal layer with a photoresist layer;

exposing said photoresist layer with a controlled laser beam in a selective pattern;

applying developer to said photoresist layer to remove unexposed photoresist from said photoresist layer;

etching said metal layer through said photoresist layer; and

removing said photoresist layer.

4. A method for interconnecting integrated circuits as recited in claim 3 wherein the step of applying a metal layer comprises the steps of sputtering a first metal onto said dielectric layer and electroplating a second metal onto the sputtered first metal.

5. A method for interconnecting integrated circuits as recited in claim 3 wherein the step of applying developed to said photoresist layer comprises spraying said developer onto said photoresist layer.

6. A method for interconnecting integrated circuits at a very high density, comprising the steps of:

fabricating a plurality of substrates, each respective substrate having an integrated circuit thereon and edge contact pads at an edge thereof, and on each respective substrate said integrated circuit and said edge contact pads being electrically connected, each of said substrates including apertures extending completely therethrough;

coating a top and bottom surface of each of said substrates, respectively, with a thermal grease;

stacking said substrates in a vertical configuration such that for any adjacent pair of substrates the top surface of one substrate of said pair and the bottom surface of the other substrate of said pair abut, in common, a layer of said thermal grease and such that said apertures of the stacked substrates align through the stacked vertical configuration of substrates;

joining said stacked substrates with fasteners extending through said apertures of said substrates to form a stacked module;

applying a dielectric layer to a side of said stacked module;

forming vias through said dielectric layer to join with said edge contact pads on said substrates in said stacked module; and

creating an interconnect pattern on said electric layer, said interconnect pattern being electrically connected to said edge contact pads by electrically contacting said vias in said dielectric layer, said interconnect pattern thereby electrically interconnecting in a predetermined manner the integrated circuits on said substrates in said stacked module.

7. A method for interconnecting integrated circuits as recited in claim 6 wherein the step of applying a dielectric layer to a side of said stacked module comprises the steps of spraying an adhesive onto said side of said stacked module and then applying a dielectric film under pressure to said side of said stacked module.

8. A method for interconnecting integrated circuits as recited in claim 6 wherein the step of applying a dielectric layer to a side of said stacked module comprises the step of laminating said dielectric layer to said side.

9. A method for interconnecting integrated circuits as recited in claim 6 wherein said integrated circuits are mounted in chip wells and are bonded to said substrate by an adhesive, said substrates having a relatively flat profile to allow for tight stacking.

10. A method for interconnecting integrated circuits as recited in claim 9 wherein the step of forming vias comprises laser dithering holes through said dielectric layer, and sputtering metal onto said dielectric layer so as to fill said holes.

11. A method for interconnecting integrated circuits as recited in claim 9 wherein the step of creating an interconnect pattern comprises the steps of:

applying a metal layer on said dielectric layer;

coating over said metal layer with a photoresist layer;

exposing said photoresist layer with a controlled laser beam in a selective pattern;

spraying developer on said photoresist layer to remove unexposed photoresist from said photoresist layer;

etching said metal layer through said photoresist layer; and

removing said photoresist layer.

12. A method for interconnecting integrated circuits as recited in claim 10 wherein the step of applying a metal layer comprises the steps of sputtering a first metal onto said dielectric layer and electroplating a second metal onto the sputtered first metal.

13. A method for interconnecting integrated circuits at a very high density, comprising the steps of:

fabricating a plurality of substrates, each respective substrate having an integrated circuit thereon and edge contact pads at an edge thereof, and on each respective substrate said integrated circuit and said edge contact pads being electrically connected, each of said substrates being of dimensions that are different from one another;

coating a top and bottom surface of each of said substrates, respectively, with an adhesive;

stacking said substrates in a configuration such that for any adjacent pair of substrates said adhesive bonds the top surface of one substrate of said pair to the bottom surface of the other substrate of said pair so as to form a stacked module wherein the lowermost substrate has the largest dimensions of said plurality of substrates and progressively smaller substrates are stacked thereon, said edge contact pads on each respective substrate in said stacked module being exposed at their uppermost surfaces, respectively; and

selectively bonding said edge contact pads to wires in accordance with a predetermined interconnection configuration.

14. A method for interconnecting integrated circuits at a very high density, comprising the steps of:

fabricating a plurality of modules, each respective module having an integrated circuit thereon and contact pads on a surface thereof, and on each respective substrate said integrated circuit and said contact pads being electrically connected;

arranging said modules in a two-dimensional array such that said each respective surface of said modules faces in a common direction;

bonding a polymer overlay layer onto said modules in said two-dimensional array so as to contact said each respective surface;

forming apertures through said polymer overlay layer to expose said contact pads;

coating said polymer overlay layer with metal so as to fill said apertures in said polymer overlay layer with said metal and produce a metal layer on said polymer overlay layer; and

patterning said metal layer to create an interconnect pattern which electrically connects said integrated circuits on said modules in a predetermined manner.

15. A method for interconnecting integrated circuits as recited in claim 14 wherein each respective one of said modules comprises a plurality of substrates joined together in a stack, each respective one of said substrates having electrical components positioned thereon, a second polymer overlay layer adhesively bonded to a side of each respective stack of said substrates, and a second interconnect pattern formed on said second polymer overlay layer electrically connecting in a predetermined manner said electrical components in the stack.

16. A method of repairing a stack of interconnected integrated circuits, said stack comprising a plurality of substrates in a stacked configuration, each of said substrates having an integrated circuit positioned thereon, respectively;

electrical connection means on each of said substrates, respectively, for providing electrical connection sites on a side of said stacked configuration of said plurality of substrates, said electrical connection means on each of said substrates, respectively, being electrically connected to said integrated circuit positioned thereon, respectively;

holding means for holding said substrates together in said stacked configuration;

a thermoplastic dielectric layer laminated to said side of said stacked configuration; and

a metal interconnect pattern situated on said thermoplastic dielectric layer, said electrical connection sites being electrically connected to said interconnect pattern by metal-filled vias in said thermoplastic dielectric layer, said method comprising;

heating said thermoplastic dielectric layer to a temperature only sufficiently high to allow its removal from said side of said stacked configuration;

replacing any defective one of said substrates in said stacked module;

applying a new dielectric layer onto said side of said stacked configuration;

forming apertures through said new dielectric layer to expose said electrical connection sites;

applying a metal layer onto said new dielectric layer, said metal layer filling said apertures and contacting the exposed electrical connection sites; and

patterning said metal layer to form said interconnect pattern.

17. The method of repairing a stack of interconnected integrated circuits of claim 16 wherein said new dielectric layer comprises a thermoplastic film.

18. A method of repairing an array of interconnected integrated circuits, said integrated circuits comprising a plurality of modules situated in a two-dimensional array, each of said modules having an integrated circuit respectively positioned thereon and further having an electrical connection site respectively situated on a surface thereof, said surface of each respective module in said array facing in a common direction, each of said modules further including electrical connection means respectively situated thereon for electrically connecting said integrated circuit respectively situated thereon with said electrical connection site respectively situated on said surface thereof;

a polymer overlay layer extending over said plurality of modules in said array and extending over each of the surfaces and said electrical connection sites on said surfaces, said polymer overlay layer having openings therein exposing said electrical connection sites;

a thermoplastic adhesive bonding said polymer overlay layer to said plurality of modules in said array and to said surfaces; and

a metal interconnect pattern on said polymer overlay layer for selectively interconnecting said electrical connection sites, said interconnect pattern including metal portions extending through said openings in said polymer overlay layer so as to make electrical connection to said electrical connection sites, said method comprising;

heating said thermoplastic adhesive to a temperature only sufficiently high to allow removal of said polymer overlay layer from said plurality of modules in said array and from said surfaces;

replacing any defective one of said modules in said array;

applying additional thermoplastic adhesive to said plurality of modules in said array and to said surfaces;

applying a new polymer overlay layer onto said plurality of modules in said array and onto said surfaces so as to become bonded thereto by said thermoplastic adhesive;

forming apertures through said new polymer overlay layer to expose said electrical connection sites;

applying a metal layer onto said new polymer overlay layer, said metal layer filling said apertures and contacting the exposed electrical connection sites; and

patterning said metal layer to form said interconnect pattern.