×

Method of making a recessed gate MOSFET device structure

  • US 5,108,937 A
  • Filed: 02/01/1991
  • Issued: 04/28/1992
  • Est. Priority Date: 02/01/1991
  • Status: Expired due to Term
First Claim
Patent Images

1. A method of producing an improved field effect transistor integrated circuit device in a silicon semiconductor substrate embodying a first P-type dopant and having a recessed gate electrode and self-aligned source and drain regions, the improvement comprising:

  • forming a first composite masking layer of a surface layer of silicon oxide and an overlying layer of silicon nitride on the surface of said semiconductor substrate that is capable of masking the underlying silicon against oxidation;

    removing portions of said first composite masking layer to form openings of exposed silicon that at least define the gate electrode regions;

    oxidizing the exposed silicon to produce a sunken silicon oxide layer;

    removing said silicon nitride layer of said composite first masking layer;

    introducing an N-type dopant into said substrate on opposite sides of the sunken thick oxide layer that defines the region of the gate electrode to form source and drain regions;

    said N-type dopant including both arsenic and phosphorous ions and annealing to cause penetration into the substrate to unequal depths, the surface concentration in the range of 1×

    1014 and 1×

    1017 atoms per cubic centimeter;

    removing said silicon oxide layer of said composite first masking layer;

    selectively removing the sunken oxide layer, thereby forming a depression in the substrate that defines the gate region, having a depth in the range of 200 to 2000 nanometers;

    forming a thin oxide layer over the source and drain regions and in the depression in the said substrate;

    forming a conductive gate electrode layer on the surface of said substrate, selectively removing portions of said conductive layer to form the gate electrode in the said depression;

    forming an insulating layer over the gate electrode;

    and forming electrical contacts and metallurgy lines with appropriate passivation, and connecting the elements of the said transistor by these contacts and lines to form said integrated circuit device.

View all claims
  • 1 Assignment
Timeline View
Assignment View
    ×
    ×