Method of making a recessed gate MOSFET device structure

• US 5,108,937 A
• Filed: 02/01/1991
• Issued: 04/28/1992
• Est. Priority Date: 02/01/1991
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsai, Yu-Hsein, Hsu, Shun-Liang
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US07/649,550
• Time in Patent Office: 452 Days
• Field of Search: 437/40, 437/41, 437/45, 437/913, 437/69, 437/203, 437/154, 437/29
• US Class Current: 438/282
• CPC Class Codes: H01L 29/66613 with a gate recessing step, e.g. using local oxidation making recessed gate LDMOS transistors H01L29/66704
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: Y10S 148/053 Field effect transistors fets

Abstract

A method of producing an improved field effect transistor integrated circuit device in a semiconductor substrate embodying a first type dopant and having a recessed gate electrode and self-aligned source and drain regions can be made. A first masking layer is formed on the surface of said semiconductor substrate that is capable of masking the underlying silicon against oxidation. Portions of first masking layer is removed to form openings that at least define the gate electrode regions. The resultant exposed silicon area are oxidized to produce a thick sunken silicon oxide layer. The first masking layer is removed. A second opposite type dopant is introduced into the substrate on opposite sides of the sunken thick oxide layer that defines the region of the gate electrode to form source and drain regions. The sunken thick oxide layer is selectively removed, thereby forming a depression in the substrate that defines the gate region. A thin oxide layer is formed over the source and drain regions, and in the depression in the said substrate. A conductive gate electrode layer is formed on the surface of substrate. Portions of the conductive layer are selectively removed to form the gate electrode in the depression. An insulating layer is formed over the gate electrode. Electrical contacts and metallurgy lines with appropriate passivation are formed. The elements of the transistor are connected by these contacts and lines to form the integrated circuit device.

Claims

1. A method of producing an improved field effect transistor integrated circuit device in a silicon semiconductor substrate embodying a first P-type dopant and having a recessed gate electrode and self-aligned source and drain regions, the improvement comprising:

forming a first composite masking layer of a surface layer of silicon oxide and an overlying layer of silicon nitride on the surface of said semiconductor substrate that is capable of masking the underlying silicon against oxidation;

removing portions of said first composite masking layer to form openings of exposed silicon that at least define the gate electrode regions;

oxidizing the exposed silicon to produce a sunken silicon oxide layer;

removing said silicon nitride layer of said composite first masking layer;

introducing an N-type dopant into said substrate on opposite sides of the sunken thick oxide layer that defines the region of the gate electrode to form source and drain regions;

said N-type dopant including both arsenic and phosphorous ions and annealing to cause penetration into the substrate to unequal depths, the surface concentration in the range of 1×

10¹⁴ and 1×

10¹⁷ atoms per cubic centimeter;

removing said silicon oxide layer of said composite first masking layer;

selectively removing the sunken oxide layer, thereby forming a depression in the substrate that defines the gate region, having a depth in the range of 200 to 2000 nanometers;

forming a thin oxide layer over the source and drain regions and in the depression in the said substrate;

forming a conductive gate electrode layer on the surface of said substrate, selectively removing portions of said conductive layer to form the gate electrode in the said depression;

forming an insulating layer over the gate electrode;

and forming electrical contacts and metallurgy lines with appropriate passivation, and connecting the elements of the said transistor by these contacts and lines to form said integrated circuit device.

2. The method of claim 1 wherein the openings in said first layer also define regions of field oxide.

3. The method of claim 1 wherein the said arsenic ions form an N+ surface region and the said phosphorous ions form a N- region below said N+ surface region to provide a lightly doped drain structure device.

4. The method of claim 3 wherein the average dopant concentration in said N+ surface region is between about 1×

10¹⁸ to 1×

10²¹ atoms per cubic cm. and the average dopant concentration in said N- region is between about 1×

10¹⁶ to 1×

10¹⁹ atoms per cubic cm.

5. The method of claim 1 wherein the conductive gate electrode layer and contacts to the source/drain regions are formed simultaneously from a metal.

6. The method of claim 5 wherein the said metal is aluminium.