Sinusoidal signal generator
First Claim
1. A complementary MOS integrated circuit comprising:
- a first circuit means for generating a sinusoidal waveform signal, said first circuit means including a plurality of complementary pairs of FET devices coupled in cascade between an input node (Vin) and an an output node (Vout);
delay means operatively coupled between the input node and the output node;
said delay means receiving an input signal provided at the input node and sequentially delaying the input signal before it is applied to a selected FET device in each of the complementary pairs of FET devices; and
a second circuit means operatively coupled between the input node and the output node;
said second circuit means responsive to the input signal to generate therefrom control signals that simultaneously inhibit conduction of non-selected FET devices.
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Accused Products
Abstract
A high current CMOS circuit including a raised cosine signal generator for generating a raised cosine signal waveform and an input circuit arrangement for controlling the raised cosine signal generator is described. The raised cosine signal generator includes an output node to which a controlled chain of CMOS inverters are connected. The input circuit arrangement accepts an input signal, converts it into appropriate signals which drive respective inverters so that simultaneous conduction of inverter pairs is prevented. The off chip driver (OCD) minimizes ground bounce, electrical noise and radiation problems caused by large current transients or spikes (di/dt) that usually accompany such circuits.
17 Citations
18 Claims
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1. A complementary MOS integrated circuit comprising:
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a first circuit means for generating a sinusoidal waveform signal, said first circuit means including a plurality of complementary pairs of FET devices coupled in cascade between an input node (Vin) and an an output node (Vout); delay means operatively coupled between the input node and the output node;
said delay means receiving an input signal provided at the input node and sequentially delaying the input signal before it is applied to a selected FET device in each of the complementary pairs of FET devices; anda second circuit means operatively coupled between the input node and the output node;
said second circuit means responsive to the input signal to generate therefrom control signals that simultaneously inhibit conduction of non-selected FET devices. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A CMOS circuit arrangement for generating a sinusoidal waveform comprising:
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an input node (Vin) for receiving an input signal; an output node (Vout) for generating an output signal; a plurality of inverter circuit means coupled in tandem between the input node and the output node; and a plurality of transfer gates connected in tandem and coupled to the input node, with each transfer gate in the plurality of transfer gates operatively coupled to selected ones of the plurality of inverter circuit means;
said each transfer gate delaying the input signal to the selected ones of the plurality of series connected inverter circuit means to cause said selected ones of the plurality of series connected inverter circuit means to switch sequentially to provide the sinusoidal waveform at the output node. - View Dependent Claims (10, 11, 12, 13, 14, 15, 17)
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16. An improved CMOS integrated circuit comprising:
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a signal input terminal; a signal output terminal; an output circuit means for generating a sinusoidal waveform signal coupled between the signal output terminal and the signal input terminal, said output circuit means including a plurality of PFET and NFET inverter pairs connected in cascade; a plurality of transfer gates connected in tandem between the signal input terminal and signal output terminal with different ones of the transfer gates connected to PFET and NFET devices of each inverter pair; and a control means coupling an input signal at the signal input terminal to each one of the plurality of the PFET and NFET inverter pairs said control means responsive to signal at the data input terminal to inhibit conduction of PFET devices in the plurality of inverter pairs when one NFET device is conducting and to inhibit conduction of NFET devices in the plurality of inverter pairs when one PFET device is conducting. - View Dependent Claims (18)
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Specification