Multiprocessing method and arrangement

• US 5,109,329 A
• Filed: 02/06/1987
• Issued: 04/28/1992
• Est. Priority Date: 02/06/1987
• Status: Expired due to Fees

• Current Assignee: American Telephone & Telegraph Company (AT&T, Inc.), AT&T Information Systems Inc. (AT&T, Inc.)
• Original Assignee: AT&T, Inc.
• Inventors: Strelioff, Brian K.
• Primary Examiner(s): Fleming, Michael R.
• Assistant Examiner(s): CHUN, DEBRA
• Application Number:
  US07/012,085
• Time in Patent Office: 1,908 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/300, 364/200, 364/900, 371/9, 371/11, 371/8.1, 371/9.1, 371/11.1, 371/11.3
• US Class Current: 710/261
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system

Abstract

A master-slave multiprocessor (FIG. 1) is formed by connecting a slave processor (25) to an I/O slot of a uniprocessor, and by minimally modifying the uniprocessor'"'"'s operating system. At initialization, one routine (FIG. 5) redirects slave interrupt vectors (200) to point to a common interrupt handler (FIG. 12). Before a process executes on the slave processor, another routine (FIGS. 9 and 10) corrupts execution stack bounds (217, 218) of the process. A non-interrupt operating system call during execution of the process causes an automatic firmware check (FIG. 3) of the execution stack pointer (203) against the stack bounds. Occurrence of an interrupt or encounter of a stack exception results in suspension of process execution and invocation of the interrupt handler or a slave stack exception handler (FIG. 11), respectively. Each handler calls a slave delete routine (FIG. 15) to restore the process'"'"' stack bounds to valid values and to transfer the process for execution to the master processor (12). On the master processor, process execution resumes at the point of suspension, and the operating system service required by the system call or interrupt is carried out.

Claims

1. A method for use in a multiprocessor system having a first and a second processor and a plurality of means each for pointing to a procedure to be executed in response to an occurrence of an event to which the means corresponds, wherein execution mode changes from a user mode for executing user program instructions to a privileged mode for executing operating system instructions in response to occurrence of any one of a plurality of events, the method comprising the steps of:

executing a process in the user execution mode in the first processor;

changing from the user execution mode to the privileged execution mode in the first processor, in response to the occurrence in the first processor of any one of the plurality of events;

executing in the privileged execution mode in the first processor a first procedure pointed to by first means of the plurality of pointing means, the first means corresponding in the first processor to at least the occurred one of the plurality of events; and

transferring the process from the first processor to the second processor for continued execution, by the execution of the first procedure, wherein execution of the procedure pointed to be the pointing means corresponding in the first processor to any one of the plurality of events transfers the process from the first processor to the second processor for continued execution.

2. The method of claim 1 further comprising the steps of:

entering the privileged execution mode in the second processor;

executing in the privileged execution mode in the second processor a second procedure pointed to be second means of the plurality of pointing means, the second means corresponding in the second processor to at least the occurred one of the plurality of events; and

processing the occurred event by the execution of the second procedure, wherein execution of the procedure pointed to be the pointing means corresponding in the second processor to any one of the plurality of events processes the corresponding event.

3. The method of claim 2 wherein the step of entering the privileged execution mode in the second processor comprises the steps of:

executing the transferred process in the user execution mode in the second processor; and

changing from the user execution mode to the privileged execution mode in the second processor, in response to occurrence in the second processor of the event that previously occurred in the first processor.

4. The method of claim 2 in a system wherein the plurality of events comprise interrupts or exceptions;

wherein

the pointing means comprise interrupt or exception vectors;

wherein

the pointing means corresponding to the plurality of events in the first processor comprise vectors corresponding to interrupts or exceptions on the first processor that have been redirected from pointing to procedures for handling the corresponding interrupts or exceptions to pointing to the first procedure; and

wherein

examining the pointing means corresponding to the plurality of events in the second processor comprise interrupt or exception vectors corresponding to interrupts or exceptions on the second processor that point to the procedures for handling the corresponding interrupts or exceptions.

5. In a multiprocessor system having a first and a second processor and a plurality of interrupt vectors each pointing to an interrupt handler to be executed in response to an occurrence of an interrupt to which the interrupt vector corresponds, wherein execution mode changes from a user mode for executing user program instruction to a privileged mode for executing operating system instructions in response to occurrence of any one of a plurality of interrupts, a method of operation comprising the steps of:

executing a process in the user execution mode in the first processor,

detecting occurrence of one of the plurality of interrupts during execution of the process;

changing from the user execution mode to the privileged execution mode in the first processor, in response to the occurrence in the first processor of any one of the plurality of interrupts;

executing in the privileged execution mode in the first processor a first interrupt handler pointed to by a first interrupt vector that corresponds to the occurred interrupt in the first processor, the first interrupt vector being one of a plurality of first interrupt vectors each corresponding to a different one of the plurality of interrupts in the first processor, the plurality of first interrupt vectors all pointing to the first interrupt handler; and

transferring the process from the first processor to the second processor for continued execution, by the execution of the first interrupt handler, wherein entry of privileged execution mode;

during execution of a process in the first processor results in transfer of the process to the second processor for continued execution.

6. The method of claim 5 further comprising the steps of:

entering the privileged execution mode in the second processor;

executing in the privileged execution mode in the second processor a second interrupt handler pointed to be a second interrupt vector that corresponds to the occurred interrupt in the second processor, the second interrupt vector being one of a plurality of interrupt vectors each corresponding to a different one of the plurality of interrupts in the second processor; and

processing the occurred interrupt by the execution of the second interrupts handler, wherein execution of an interrupt handler pointed to by the interrupt vector corresponding in the second processor to any one of the plurality of interrupts processes the corresponding interrupt.

7. The method of claim 6 wherein the step of entering the privileged execution mode in the second processor comprises the steps of:

starting execution of the transferred process in the second processor at a point at which execution stopped on the first processor.

8. The method of claim 7 wherein the step of entering the privileged execution mode in the second processor comprises the further step of

changing from the user execution mode to the privileged execution mode in the second processor, in response to occurrence of the interrupt that previously occurred on the first processor during execution of the transferred process on the second processor.

9. A multiprocessor system comprising:

a first and a second processor each operable in either one of a user execution mode for executing user program instructions and a privileged execution mode for executing operating system instructions;

a plurality of means each for pointing to a procedure to be executed in response to an occurrence of an event to which the means corresponds, wherein execution of a procedure pointed to be the pointing means corresponding in the first processor to any one of a plurality of events transfers a process executing in the first processor to the second processor for continued execution;

means in the first processor for executing a process in the user execution mode and for executing a procedure pointed to be the pointing means in the privileged execution mode; and

means in the first processor for causing the executing means to execute a first procedure pointed to be first pointing means of the plurality of pointing means, in response to occurrence in the first processor of one of the plurality of events, the first pointing means corresponding in the first processor to at least the occurred one of the plurality of events, to transfer the process from the first processor to the second processor for continued execution.

10. The system of claim 9 wherein

execution of a procedure pointed to be the pointing means corresponding in the second processor to any one of the plurality of events processes the corresponding event;

the system further comprising

means in the second processor for executing the transferred process in the user execution mode and for executing a procedure pointed to be the pointing means in the privileged execution mode, and

means in the second processor for causing the executing means in the second processor to execute a second procedure pointed to be second pointing means of the plurality of pointing means, the second pointing means corresponding in the second processor to at least the occurred one of the plurality of events, to process the occurred event in the second processor.

11. The system of claim 10 wherein

the causing means in the second processor comprise

means for causing the executing means in the second processor to execute the second procedure in response to occurrence in the second processor of the event that previously occurred in the first processor.

12. The system of claim 10 wherein

the plurality of events comprise interrupts or exceptions;

wherein

the pointing means comprise interrupt or exception vectors;

wherein

the pointing means corresponding to the plurality of events in the first processor comprise vectors corresponding to interrupts or exceptions on the first processor that have been redirected from pointing to procedures for handling the corresponding interrupts or exceptions to pointing to the first procedure; and

wherein

the pointing means corresponding to the plurality of events in the second processor comprise

interrupt of exception vectors corresponding to interrupts or exceptions on the second processor that point to the procedures for handling the corresponding interrupts or exceptions.

13. A multiprocessor system comprising:

a first and a second processor each operable in either one of a user execution mode for executing user program instructions and a privileged execution mode for executing operating system instructions;

a plurality of means each for pointing to a procedure to be executed in response to an occurrence of an event to which the means corresponds, wherein execution of the procedure pointed to be the pointing means corresponding in the first processor to any one of a plurality of events transfers a process executing in the first processor to the second processor for continued execution;

means in the first processor for executing a process in the user execution mode;

means in the first processor for changing operation from the user execution mode to the privileged execution mode in response to the occurrence in the first processor of any one of the plurality of events; and

means in the first processor for executing in the privileged execution mode a first procedure pointed to be first pointing means of the plurality of pointing means, the first pointing means corresponding in the first processor to at least the occurred one of the plurality of events, to transfer the process from the first processor to the second processor for continued execution.

14. The system of claim 13 wherein

execution of the procedure pointed to by the pointing means corresponding in the second processor to any one of the plurality of events processes the corresponding event;

the system further comprising

means in the second processor for executing in the privileged execution mode a second procedure pointed to be second pointing means of the plurality of pointing means, the second pointing means corresponding in the second processor to at least the occurred one of the plurality of events, to process the occurred event in the second processor,

means in the second processor for changing operation from the privileged execution mode to the user execution mode in response to completion of processing of the occurred event, and

means in the second processor for executing the transferred process in the user execution mode.

15. The system of claim 14 wherein the operation changing means further comprise

means for changing operation from the user execution mode to the privileged execution mode in response to occurrence in the second processor of the event that previously occurred in the first processor.

16. A multiprocessor system comprising:

a first and a second processor wherein execution mode changes from a user mode for executing user program instructions to a privileged mode for executing operating system instructions in response to occurrence of any one of a plurality of interrupts;

a first interrupt handler whose execution transfers a process executing at occurrence of an interrupt in the first processor to the second processor for continued execution;

a plurality of interrupt vectors each pointing to an interrupt handler to be executed in response to an occurrence of an interrupt to which the interrupt vector corresponds;

means in the first processor, for executing processes in the user execution mode and for executing interrupt handlers pointed to be the interrupt vectors in the privileged execution mode;

means in the first processor responsive to occurrence in the first processor of one of a plurality of interrupts, for causing the executing means to execute an interrupt handler pointed to by a first interrupt vector that corresponds to the occurred interrupt in the first processor, the first interrupt vector being one of a plurality of first interrupt vectors each corresponding to a different on of the plurality of interrupts in the first processor, the plurality of first interrupt vectors all pointing to the first interrupt handler, wherein entry of privileged execution mode during execution of a process in the first processor results in transfer of the process to the second processor for continued execution.

17. The system of claim 16 further comprising:

a plurality of second interrupt handlers each for processing an interrupt;

means in the second processor for executing processes in the user execution mode and for executing interrupts handlers pointed to be the interrupt vectors in the privileged execution mode;

means in the second processor for causing the executing means in the second processor to execute an interrupt handler pointed to be a second interrupt vector that corresponds to the occurred interrupt in the second processor, the second interrupt vector being one of a plurality of second interrupt vectors corresponding to ones of the plurality of interrupts in the second processor and pointing to one of the second interrupt handlers,

wherein execution in the second processor of a second interrupt handler pointed to by an interrupt vector corresponding in the second processor to any one of the plurality of interrupts processes the corresponding interrupt.

18. The system of claim 17 wherein

the causing means in the second processor are responsive to occurrence of the interrupt that previously occurred on the first processor during execution of the transferred process by the executing means in the second processor, for causing the executing means in the second processor to execute the second interrupt handler pointed to by the second interrupt vector that corresponds to the occurred interrupt in the second processor.