Silicon membrane with controlled stress

• US 5,110,373 A
• Filed: 08/09/1990
• Issued: 05/05/1992
• Est. Priority Date: 09/13/1988
• Status: Expired due to Fees

• Current Assignee: Nanostructures, Inc.
• Original Assignee: Nanostructures, Inc.
• Inventors: Mauger, Philip E.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): FOURSON III, GEORGE R
• Application Number:
  US07/565,253
• Time in Patent Office: 635 Days
• Field of Search: 156/628, 156/657, 437/225, 437/901, 437/966, 437/974, 437/86, 148/DIG. 135, 148/DIG. 159, 357/26
• US Class Current: 148/33.2
• CPC Class Codes: B81B 2203/0127 Diaphragms, i.e. structures separating two media that can control the passage from one medium to another; Membranes, i.e. diaphragms with filtering function
• CPC Class Codes: B81C 1/00666 Treatments for controlling internal stress or strain in MEMS structures
• CPC Class Codes: B81C 2201/0164 by doping the layer
• CPC Class Codes: C23C 14/0005 Separation of the coating from the substrate
• CPC Class Codes: C25F 3/12 of semiconducting materials
• CPC Class Codes: H01L 21/3063 Electrolytic etching
• CPC Class Codes: Y10S 148/159 Strain gauges
• CPC Class Codes: Y10S 438/938 Lattice strain control or utilization
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

A method for fabricating a silicon membrane with predetermined stress characteristics. A silicon substrate is doped to create a doped layer as thick as the desired thickness of the membrane. Stress within the doped layer is controlled by selecting the dopant based on its atomic diameter relative to silicon and controlling both the total concentration and concentration profile of the dopant. The membrane is then formed by electrochemically etching away the substrate beneath the doped layer.

Claims

1. A stress-controlled silicon structure having a membrane comprising:

a silicon substrate with a first electrical conductivity type, said substrate having first and second opposite surfaces;

a doped layer adjacent to said first surface of said substrate having a dopant with a second electrical conductivity type, said doped layer having a non-uniform dopant concentration profile that varies as a function of lateral position on said first surface; and

an electrochemically etched portion of said second surface of said substrate etched to a boundary of said doped layer, thereby forming said membrane with a thickness approximately equal to the thickness of said doped layer, said membrane having a pattern of internal stress that varies in accordance with the dopant concentration profile.

2. The silicon structure of claim 1 wherein said pattern of internal stress is tensile stress and wherein said dopant is selected from the group consisting of boron and phosphorus.

3. The silicon structure of claim 1 wherein said pattern of internal stress is compressive stress and wherein said dopant is selected from the group consisting of antimony and tin.