Incorporation of dielectric layers in a semiconductor

• US 5,110,712 A
• Filed: 04/25/1990
• Issued: 05/05/1992
• Est. Priority Date: 06/12/1987
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Wu, Robert W., Kessler, Daniel D., Beatty, Christopher C., Crook, Mark D.
• Primary Examiner(s): Bowers, Jr., Charles L.
• Assistant Examiner(s): NEVILLE, THOMAS
• Application Number:
  US07/547,093
• Time in Patent Office: 741 Days
• Field of Search: 430/312, 430/313, 430/314, 430/316, 430/317, 427/96, 427/99, 156/643
• US Class Current: 438/623
• CPC Class Codes: H01L 21/31138 by dry-etching
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics

Abstract

A system for integrating a composite dielectric layer in an integrated circuit to facilitate fabrication of a high density multi-level interconnect with external contacts. The composite dielectric layer comprises of a polymer layer which normally comprises a polyimide that is deposited using conventional spin-deposit techniques to form a planarized surface for deposition of an inorganic layer typically comprising silicon dioxide or silicon nitride. The inorganic layer is etched using standard photoresist techniques to form an inorganic mask for etching the polymer layer. A previously deposited inorganic layer functions as an etch stop to allow long over etches to achieve full external contacts which, in turn, allows high density interconnect systems on multiple levels.

Claims

1. A process for forming a composite dielectric sandwich in an integrated circuit through the use of inorganic dielectric layers comprising the steps of:

(a) forming a first inorganic dielectric layer over at least one underlying layer of said integrated circuit that has sufficient strength to protect said underlying layer by distributing stress from subsequently formed metal features that are deposited on said first inorganic dielectric layer;

(b) forming first metal features on said first inorganic dielectric layer;

(c) forming a polymer layer over said first inorganic dielectric layer and said first metal features of said integrated circuit, said polymer layer being substantially uniformly distributed to provide a substantially planarized surface;

(d) depositing a second inorganic dielectric layer in said integrated circuit over said polymer layer that provides sufficient strength to protect said polymer layer by distributing stress from subsequently formed second metal features that are deposited on said second inorganic dielectric layer;

(e) forming a mask on said second inorganic dielectric layer;

(f) etching said second inorganic dielectric layer using said mask as a masking pattern to form an inorganic dielectric mask and to provide a protective layer for etching of any subsequently deposited polymer layers;

(g) etching said polymer layer using said inorganic dielectric mask as a masking pattern to essentially remove all polymer unmasked by said inorganic dielectric mask between said inorganic dielectric mask and said first inorganic dielectric layer such that said first inorganic dielectric layer functions as a protective layer and etch stop for said underlying layers wherever said etching of said polymer layer continues after all of said unmasked polymer has been removed to fully expose any existing external contact surfaces of said first metal features;

(h) maintaining said second inorganic dielectric layer as an insulating layer that, together with said polymer layer, forms said composite dielectric sandwich that has sufficient strength to distribute stress from subsequently formed second metal features and that remains in said integrated circuit as an etch stop layer for subsequently formed layers in a multilayer integrated circuit;

(i) forming said second metal features on said second inorganic dielectric layer an in vias formed by etching said polymer layer.

2. The process of claim 1 wherein said step of forming said polymer layer comprises the steps of:

depositing a polymer suspended in a solvent on said first inorganic dielectric layer;

uniformly distributing said polymer suspended in said solvent by spinning said integrated circuit;

thermally curing said polymer to remove said solvent.

3. The process of claim 1 wherein said step of depositing said second inorganic dielectric layer comprises the step of applying silicon dioxide using plasma enhanced chemical vapor deposition.

4. The process of claim 1 wherein said step of depositing said second inorganic dielectric layer comprises the step of applying silicon dioxide using atmospheric pressure deposition.

5. The process of claim 1 wherein said step of forming a mask on said second inorganic dielectric layer comprises:

depositing a photoresist layer on said second inorganic dielectric layer that is highly planarized so that small features can be transferred to said polymer layer;

exposing said photoresist layer using photolithographic techniques with a predetermined masking pattern;

etching said photoresist layer to produce a photoresist mask essentially corresponding to said predetermined masking pattern.

6. The process of claim 1 wherein said step of etching said second inorganic dielectric layer comprises the step of dry etching said second inorganic dielectric layer with carbon tetraflouride in a reactive ion etcher.

7. The process of claim 1 wherein said step of etching said polymer layer comprises dry etching said polymer layer with oxygen noble gas ions in a reactive ion etcher.

8. The process of claim 1 wherein said underlying layers of said integrated circuit comprise at least one composite dielectric layer formed in accordance with steps (a) through (h) of claim 1 and said first inorganic layer is formed such that the manner of deposition, the thickness and the composition of said first inorganic layer are chosen to be compatible with an underlying polymer layer that is deposited over said at least one underlying layer of said integrated circuit such that said first inorganic layer provides the required strength to distribute stress from said first metal features that are deposited on said first inorganic layer that are formed from a highly stressed metal layer.

9. The process of claim 1 wherein said step of depositing said second inorganic dielectric layer comprises using plasma enhanced chemical vapor deposition such that sad second inorganic dielectric layer is placed in compressive stress to compensate for tensile stress of subsequently deposited metal layers.