Roughened polysilicon surface capacitor electrode plate for high denity dram

• US 5,110,752 A
• Filed: 07/10/1991
• Issued: 05/05/1992
• Est. Priority Date: 07/10/1991
• Status: Expired due to Term

• Current Assignee: Industrial Technologyy
• Original Assignee: Industrial Technology Research Institute
• Inventors: Lu, Chih-Yuan
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): OJAN, OURMAZD
• Application Number:
  US07/727,873
• Time in Patent Office: 300 Days
• Field of Search: 437/47, 437/48, 437/52, 29/25.03, 357/23.6
• US Class Current: 438/398
• CPC Class Codes: H01L 28/84 being a rough surface, e.g. using hemispherical grains
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: Y10S 438/964 Roughened surface

Abstract

A method of fabricating a microminaturized capacitor having an electrode that is roughened to increase the effective area per unit area and resulting structure, particularly adapted for use in high density dynamic random access memory devices. The method involves depositing a conductive polycrystalline silicon layer. The depositing a metal such as a refractory metal over the polysilicon layer. The composite layer is heated to form a metal silicide and roughened polycrystalline silicon surface while the grains also grow large. The metal silicide is removed, leaving a roughened surface. The capacitor dielectric layer is deposited upon the roughened surface. The second conductive polycrystalline silicon layer is now formed upon said dielectric layer to complete the capacitor.

Claims

1. A method to produce a roughened surface capacitor fabricated on a monocrystalline semiconductor substrate comprising:

depositing a thin first polycrystalline silicon layer to form a first capacitor plate on a particularly completed DRAM over a base insulating layer and a contact opening exposing said substrate;

doping said first polycrystalline silicon layer with an impurity for semiconductors;

depositing a thin layer of a metal capable of forming a silicide over the surface of said first layer;

heating the resultant composite layer at a temperature to cause silicidation for a time sufficient to preferentially react with grains versus grain boundaries and to grow silicon grain crystals on the surfaces to thereby producing a roughened surface;

removing the metal silicide from the resultant roughened composite layer with a suitable etchant;

depositing a thin insulating layer to form a capacitor dielectric layer over the surface of the roughened layer; and

depositing a second thin polycrystalline silicon layer over said thin insulating layer to form the second capacitor plate.

2. The method of claim 1 wherein said first polycrystalline silicon layer is doped with an impurity in a concentration of between about 10¹⁸ to 10²¹ cm³.

3. The method of claim 1 wherein said impurity is introduced into said first layer by combining it with the reactant for depositing the said first layer as the layer is deposited.

4. The method of claim 1 wherein said impurity is introduced into said first layer by ion implantation.

5. The method of claim 1 wherein said metal is a refractory metal and is titanium.

6. The method of claim 5 wherein the thickness of said layer of titanium is between about 400 to 2000 Angstroms.

7. The method of claim 5 wherein the composite layer of titanium and polycrystalline silicon is heated to a temperature between about 500°

to 1000°

C.

8. The method of claim 7 wherein said composite layer is heated for a time in the range of 10 to 180 minutes in an inert atmosphere.

9. The method of claim 5 wherein the resultant layer of titanium disilicide is removed by a buffered hydrofluoric acid solution.

10. The method of claim 1 wherein said metal is cobalt.

11. The method of claim 1 wherein said metal is tungsten.

12. The method of claim 1 wherein the thickness of said thin insulating layer is between about 30 to 250 Angstroms.

13. The method of claim 12 wherein the thin insulating layer is a composite layer of silicon oxide, silicon nitride and silicon oxide.

14. The method of claim 12 wherein the thin insulating layer at least includes tantalum oxide.

15. The method of claim 12 wherein the thickness of said second polycrystalline silicon layer is between about 500 to 3000 Angstroms.

16. The method of claim 1 wherein said roughened surface capacitor is made in combination with a field effect transistor and is adapted for use in a high density dynamic random access memory.

17. The method of claim 1 wherein following said removal of said metal silicide layer, the said first polycrystalline silicon layer is patterned as an electrode of said capacitor.