Method of making a DRAM capacitor for use as an programmable antifuse for redundancy repair/options on a DRAM

• US 5,110,754 A
• Filed: 10/04/1991
• Issued: 05/05/1992
• Est. Priority Date: 10/04/1991
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Lowrey, Tyler A., Cloud, Eugene H., Duesman, Kevin G.
• Primary Examiner(s): Thomas, Tom
• Application Number:
  US07/771,688
• Time in Patent Office: 214 Days
• Field of Search: 437/47, 437/48, 437/52, 437/60, 437/170, 437/922, 437/919, 357/45, 357/51, 365/200, 307/219
• US Class Current: 438/386
• CPC Class Codes: H01L 21/76888 By rendering at least a portion of the conductor non conductive, e.g. oxidation
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/118 Masterslice integrated circuits
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor

Abstract

The invention is directed to a concept to use a 3-dimensional DRAM capacitor as a one-time non-volatile programming element (programmable antifuse) to make redundancy repair and/or to select other options on a DRAM. The programmable element of the present invention provides some significant advantages, such as a lower programming voltage, which allows use of the DRAM'"'"'s existing operating supply, and requiring only half of the operating voltage to test the element once programming is accomplished. The lower programming voltage allows for redundancy repair of defective DRAM cells (or selecting other options) to be made after the DRAM die is packaged including after it is installed at a customer'"'"'s site.

Claims

1. A process to form a programmable 3-dimensional antifuse element in a dynamic random access memory fabricated on a starting substrate, said process comprising:

(a) forming a isolative dielectric layer over an existing surface of said starting substrate, said starting substrate surface having first and second conductors therein;

(b) masking and etching a first buried contact opening thereby exposing a portion of said first conductor;

(c) placing a first conductive material superjacent said isolative dielectric layer and said first conductor'"'"'s xposed portion thereby forming a first buried contact between said first conductive material and said first conductor'"'"'s exposed portion;

(d) patterning said first conductive material thereby leaving a patterened portion of said first conductive material aligned about said first buried contact;

(e) forming a dielectric layer superjacent said patterened first conductive material and said isolative dielectric layer;

(f) masking and etching a second buried contact opening thereby exposing a portion of said second conductor;

(g) placing a second conductive material superjacent said dielectric layer and said second conductor'"'"'s exposed portion thereby forming a second buried contact between said second conductive material and said second conductor'"'"'s exposed portion; and

(h) patterning said second conductive material thereby leaving a patterned portion of said second conductive material aligned about said contact and extending to and overlying said first conductive material, said patterned first conductive material, the portion of said patterned second conductive material overlying said first patterned conductive material and the portion of said dielectric residing therebetween forming said programmable 3-dimensional antifuse structure.

2. The process as recited in claim 1, wherein said dynamic random access memory fabrication uses stacked capacitor technology.

3. The process as recited in claim 1, wherein said dynamic random access memory fabrication uses trench capacitor technology.

4. The process as recited in claim 1, wherein said first and second conductive plates comprise conductively doped polysilicon.

5. The process as recited in claim 1, wherein said first and second conductive plates comprise a refractory metal.

6. The process as recited in claim 5, wherein said refractory metal is tantalum.

7. The process as recited in claim 5, wherein said refractory metal is titanium.

8. The process as recited in claim 1, wherein said capacitor dielectric comprises oxide.

9. The process as recited in claim 1, wherein said said capacitor dielectric is 25 to 100 Å

thick.

10. The process as recited in claim 1, wherein said capacitor dielectric comprises nitride.

11. The process as recited in claim 1, wherein said capacitor dielectric comprises a multiple layered dielectric.

12. The process as recited in claim 11, wherein said multiple layered dielectric comprises oxide/nitride/oxide layers.