Apparatus and method for demodulating a digital modulation signal
First Claim
1. A demodulating apparatus comprising:
- detector means for performing a frequency-detection on a digital modulation signal to acquire a detection signal;
clock generating means for generating a clock signal; and
discrimination means for sampling a voltage level of said detection signal from said detector means at a clock timing of said clock signal from said clock generating means, and converting the sampled voltage level into digital data, which is set to have one of first and second logic values on the basis of a reference voltage LDC;
wherein said discrimination means includes control means for comparing the voltage level En sampled at a clock timing, voltage level En-1 sampled at a timing one clock earlier than En and voltage level En-2 sampled at a timing two clock earlier than En, with first and second threshold voltages LA and LB respectively higher and lower than said reference voltage LDC, and controlling said clock generating means to synchronize the phase of said clock signal with said detection signal when it is detected from the comparison that anyone of first and second conditions is satisfied where the first condition is En-2<
LB, LB≦
En-1≦
LA and LA<
En, and the second condition is LA<
En-2,
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Abstract
A demodulating apparatus comprises a frequency detector for performing a frequency-detection on a digital modulation signal to acquire a detection signal, a clock generator for generating a clock signal, and a discrimination circuit for sampling a voltage level of the detection signal from the frequency detector at a clock timing of the clock signal from the clock generator, and converting the sampled voltage level into digital data, which is set to have one of first and second logic values on the basis of a reference voltage LDC. Particularly, the discrimination circuit includes a control circuit for comparing the voltage level En sampled at a clock timing, voltage level En-1 sampled at a timing one clock earlier than En and voltage level En-2 sampled at a timing two clock earlier than En, with first and second threshold voltages LA and LB respectively higher and lower than the reference voltage LDC, and controlling the clock generator to synchronize the phase of the clock signal with the detection signal when it is detected from the comparison that anyone of first and second conditions is satisfied where the first condition is En-2<LB, LB≦ En-1≦LA and LA<En, and the second condition is LA<En-2, LB≦En-1≦LA and En<LB.
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Citations
20 Claims
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1. A demodulating apparatus comprising:
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detector means for performing a frequency-detection on a digital modulation signal to acquire a detection signal; clock generating means for generating a clock signal; and discrimination means for sampling a voltage level of said detection signal from said detector means at a clock timing of said clock signal from said clock generating means, and converting the sampled voltage level into digital data, which is set to have one of first and second logic values on the basis of a reference voltage LDC; wherein said discrimination means includes control means for comparing the voltage level En sampled at a clock timing, voltage level En-1 sampled at a timing one clock earlier than En and voltage level En-2 sampled at a timing two clock earlier than En, with first and second threshold voltages LA and LB respectively higher and lower than said reference voltage LDC, and controlling said clock generating means to synchronize the phase of said clock signal with said detection signal when it is detected from the comparison that anyone of first and second conditions is satisfied where the first condition is En-2<
LB, LB≦
En-1≦
LA and LA<
En, and the second condition is LA<
En-2, - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A demodulating method comprising:
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a first step of performing a frequency-detection on a digital modulation signal to acquire a detection signal; a second step of generating a clock signal; a third step of sampling a voltage level of said detection signal at a clock timing of said clock signal, and converting the sampled voltage level into digital data, which is set to have one of first and second logic values on the basis of a reference voltage LDC; and a fourth step of comparing the voltage level En sampled at a clock timing, voltage level En-1 sampled at a timing one clock earlier than En and voltage level En-2 sampled at a timing two clock earlier than En, with first and second threshold voltages LA and LB respectively higher and lower than said reference voltage LDC, and controlling the phase of said clock signal to be synchronized with said detection signal when it is detected from the comparison that anyone of first and second conditions is satisfied where the first condition is En-2<
LB, LB≦
En-1≦
LA and LA<
En, and the second condition is LA<
En-2, LB≦
En-1≦
LA and En<
LB. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification
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- Resources
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Current AssigneeTokyo Electric Co., Ltd. (Toshiba Corporation)
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Original AssigneeTokyo Electric Co., Ltd. (Toshiba Corporation)
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InventorsMakino, Masaaki
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Primary Examiner(s)Pascal, Robert J.
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Application NumberUS07/730,474Time in Patent Office294 DaysField of Search329/300, 329/301, 329/302, 329/303, 329/304, 329/315, 329/318, 329/345, 375/47, 375/75, 375/80, 375/90, 375/99US Class Current329/300CPC Class CodesH04L 7/0334 Processing of samples havin...
